Point of Load converters with coupled inductors for fast transient Master’s thesis in Sustainable Electric Power Engineering and Electromobility ABHISHEK SUBRAMANAYA, BJÖRN HAVERINEN DEPARTMENT OF ELECTRICAL ENGINEERING CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2024 www.chalmers.se www.chalmers.se Master’s thesis 2024 Point of Load converters with coupled inductors for fast transient ABHISHEK SUBRAMANYA, BJÖRN HAVERINEN Department of Electrical Engineering Division of Electric Power Engineering Chalmers University of Technology Gothenburg, Sweden 2024 Point of Load converters with coupled inductors for fast transient ABHISHEK SUBRAMANYA BJÖRN HAVERINEN Department of Electrical Engineering Chalmers University of Technology © ABHISHEK SUBRAMANYA, 2024. © BJÖRN HAVERINEN, 2024. Supervisor: Ronny Hansson, Ericsson AB Examiner: Torbjörn Thiringer, Chalmers University of Technology Master’s Thesis 2024 Department of Electrical Engineering Division of Electric Power Engineering Chalmers University of Technology SE-412 96 Gothenburg Telephone +46 31 772 1000 Cover: Test board provided by Analog Devices Inc. to perform laboratory tests. Typeset in LATEX, template by Kyriaki Antoniadou-Plytaria Printed by Chalmers Reproservice Gothenburg, Sweden 2024 iv Abstract In today’s rapidly advancing technological landscape, the demand for high-speed oper- ations extends to the communication sector, necessitating faster and more responsive devices. This thesis investigates the use of various inductor topologies in multiphase buck converters, which serve as critical power supplies for numerous components. The focus is on analyzing the transient behavior of different inductor configurations to enhance current rise time. Specifically, the study compares common discrete inductors (DL), coupled in- ductors (CL), notched coupled inductors (NCL), and Trans-Inductor Voltage Regulators (TLVR) in terms of their dynamic response, output voltage ripple, and efficiency. The research is divided into two phases: • Simulation: This phase evaluates the performance of all inductor couplings, exam- ining their efficiency, dynamic response, power system rejection ratio, and stability. • Hardware Implementation: This phase focuses on two inductor couplings, DL and CL, to validate the simulation results concerning efficiency, stability, and voltage ripple through physical testing. The study was conducted with all topologies having similar stability margins. The results reveal that coupled inductors and their variants achieve higher efficiencies, with CL and NCL reaching a maximum efficiency of 95% compared to 91% for DL and TLVR. This trend was also observed in physical testing. In terms of transient performance, DL achieved the highest current slew rate of -19.59 A µs−1 during load release. The voltage and current ripples in CL and NCL contained only high-frequency components, whereas DL and TLVR exhibited both high and low-frequency components. Additionally, the PSRR was better in CL, with a gain (Vout Vin ) of 0 dB compared to DL, which had a gain of 60 dB. v Acknowledgements We would firstly like to express our gratitude to our supervisor Ronny Hansson from Er- icsson for providing guidance and feedback through the entirety of this thesis and Michael Heitmann for being very patient and supportive throughout the tenure. We would also like to thank Daniel Konieczny from Analog Devices Inc. for providing us with the test- boards and inductors and also for being both responsive and supportive. We also thank our examinor Torbjörn Thiringer for providing feedback and interest in our work with this thesis. We would like to thank Konstantinos Effraimidis, Marcus Uussalu & Lars Tillqvist for their constant support during the lab work. And lastly we want to thank our family and friends for supporting us throughout this thesis. ABHISHEK SUBRAMANYA, BJÖRN HAVERINEN, Gothenburg, 06, 2024 vi viii List of Acronyms Below is the list of acronyms that have been used throughout this thesis listed in alpha- betical order: ADI Analog Devices, Inc. CCM Continuous Conduction Mode CL Coupled Inductor DCM Discontinous Conduction Mode DL Discrete Inductor ESL Equivalent Series Inductance ESR Equivalent Series Resistance FCM Forced Continuous Mode FOM Figure of Merit FRA Frequency Response Analyzer GND Ground IC Integrated Circuit MPBC Multi-Phase Buck Converter NCL Notch Coupled Inductor OCL Open-circuit Inductance PSM Pulse-skipping mode PSRR Power System Rejection Ratio TL Trans-Inductor TLVR Trans-Inductor Voltage Regulator SM Synchronization Mode ix Contents List of Acronyms viii 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Theory 3 2.1 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1.1 Multi-phase buck converter (MPBC) . . . . . . . . . . . . . . . . . . 4 2.1.2 Discrete inductors in MPBCs . . . . . . . . . . . . . . . . . . . . . . 6 2.1.3 Output capacitors in MPBCs . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 Coupled inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4.1 Notch Coupled Inductor . . . . . . . . . . . . . . . . . . . . 9 2.1.5 Trans-inductor Voltage Regulator . . . . . . . . . . . . . . . . . . . . 9 2.2 Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Multiphase operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.4 System stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Simulation software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Case setup 15 3.1 Testboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Investigation parameters . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 Differences between simulations and testboard . . . . . . . . . . . . 18 3.2.3 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.4 Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Lab setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.2 Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Implementation 23 4.1 LT8627SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 General simulation model . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.2 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.3 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.4 Step load response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 xi Contents 4.1.5 Power system rejection . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Building & testing physical model . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.1 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.3 Voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Results 29 5.1 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 Stability Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.3 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.4 Power system rejection ratio . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.1 Stability measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.3 Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 Conclusion 43 A Simulation models I xii 1 Introduction 1.1 Background Buck converters are a type of DC/DC converter that reduce the voltage magnitude from the input to the output. They are used in a wide range of applications, such as radio systems, battery management systems, and motor controllers. The operation of a single- phase buck converter is limited by the maximum current it can provide. Higher currents can lead to decreased overall efficiency due to excessive resistive (I2R) losses, depending on application [1]. For applications with higher current demands, such as application- specific integrated circuits (ASICs) requiring currents of 600 A and current slew rates of 1200 A µs−1 [2], a single-phase buck converter may not be feasible. In these cases, multi- phase buck converters (MPBCs) may be more advantageous [1]. The increasing use of MPBCs over the past decades is driven by the rising power demands of applications such as processors [3, p. 457]. This has created a need for flexible opera- tions between low-power and high-power applications using the same converter. Conven- tional multi-phase converters with discrete inductors (DL) perform worse in low-current applications compared to single-phase buck converters [4]. The implementation of coupled inductors (CL) at the output of MPBCs is a relatively new but growing concept that en- hances the efficiency of MPBCs in low-current applications [4]. Examples of a CL setup used in MPBCs is the Notch Coupled Inductor (NCL). In a previous study at Ericsson, a comparison between the use of Trans-Inductor Voltage Regulator (TLVR) and conventional DL showed that TLVR was more beneficial [5]. In this thesis, we will conduct a comparison of CL and NCL with DL, and TLVR by simulation and physical testing. A previous study at Ericsson compared the use of TLVR and conventional DL, finding TLVR to be more beneficial [5]. In this thesis, we will compare NCL with DL in an experimental setup and in simulation. A comparison will be made to TLVR, which will only be tested through simulation. 1.2 Aim Compare the performance of a multi-phase buck converter using four different types of inductor topologies: DL, CL, NCL, and TLVR. This comparison includes efficiency, out- put voltage ripple, and load step response. Additionally, the thesis involves conducting simulation tests for all inductor topologies, and hardware tests specifically for DL and CL using test boards provided by Analog Devices Inc. (ADI). 1 1. Introduction 2 2 Theory This section aims to introduce and explain various concepts important for investigating the objective of this thesis. The buck converter is detailed for both single-phase and multi- phase implementations. Different inductor topologies are described and contrasted, and the integrated circuit (IC) to be used in simulations and on the test boards is detailed. Furthermore, system stability concepts are introduced, as they are crucial for determining the viability of a simulation model or on-board implementation. Finally, the simulation software to be used is presented. 2.1 Buck converter The buck converter is a type of DC-DC converter which transforms a given input voltage Vin to a lower output voltage Vout. The action of reducing, or stepping down, the voltage level is why the buck converter is also known as a step-down converter. The principle of operation can be explained in regards to Figure 2.1a where a purely resistive load R is used. To realize the stepping down of the voltage level to the load a switch Q is used. Neglecting losses, when Q is switched on for a time period ton Vout will equal Vin. Correspondingly when Q is switched off for a time period toff , Vout will equal zero. The total time taken for Q to change from the on- and off state to a new on-state is defined as the switching time period Ts and is the sum off ton and toff . This time period, or switching cycle, is the inverse of the switching frequency fsw which defines how many switching cycles occur during one second. The average output voltage Vout,RMS can be controlled by adjusting the duty cycle D, which defines the ratio between ton and Ts. An increase of D will lead to an increase in the average output voltage Vout,RMS ; similarly, a decrease of D will lead to a decrease in Vout,RMS . However, an implementation of this simple schematic would result in large output voltage ripples ∆Vout which may not be suitable for many applications. Hence, a more realistic schematic of the buck converter is presented in Figure 2.1b. Three additional elements are introduced: a diode d, an inductor L and a capacitor C. Assuming lossless operation, during ton both R and L are provided with Vin, and d remains reverse biased. L acts as an energy storage element so that during toff R receives current from L, and a current path is provided by d being forward-biased. C and L constitute a low- pass filter which attenuates harmonics and in turn reducing ∆Vout. Note that in practical implementations d is substituted by another switch Q. 3 2. Theory (a) (b) Figure 2.1: (a) Simplified schematic of the buck converter. (b) Complete schematic of the buck converter. There are equations of interest when considering the buck converter. One is the ratio between Vout and Vin during continuous conduction mode (CCM) which means that the inductor current iL never reaches zero which would be the case for discontinous conduction mode (DCM). The ratio between Vout and Vin is defined for CCM operation as the duty cycle D and can be expressed as Vout Vin = D (2.1) where Vout is the output voltage, Vin is the input voltage, and D is the duty cycle. Another equation of interest, which is not specific to the buck converter, is the current slew rate of the inductor di dt . This can be expressed as di dt = VL L (2.2) where di dt is the inductor current slew rate, VL is the voltage across the inductor, and L is the inductor value. (2.2) can be used to highlight why the single-phase buck converter may be unsuitable for high-current applications. Processor loads are characterised by fast transient responses, meaning that the current demand changes rapidly and di dt is high. This necessitates that an inductor provides fast di dt which requires a small inductor. In contrast, sensitive applications such as processors demand a limited output voltage ripple ∆Vout which would necessitate having a large value of L which may both increase cost and size of the inductor. Given that these attributes directly contradict each other, the single-phase buck converter may be a non-viable solution. Furthermore, for high-current applications, the single-phase buck converter can be unsuitable due to excessive resistive losses. To address these issues, the multi-phase buck converter may be a more suitable alternative [1]. 2.1.1 Multi-phase buck converter (MPBC) The MPBC is essentially a parallel connection of N single-phase buck converters where the load is shared among the converters. Each branch, or phase, is phase-shifted and shares a common voltage source. This influences the permissible duty cycle D which can be used. The sum of D for all phases should be less than or equal to 1 [3, pp. 516-517]. According to [6, p. 3], this can be expressed as 4 2. Theory D ≤ 1 N (2.3) Where D is the duty cycle, N is the number of phases. One benefit of using multiple phases as opposed to the single-phase buck converter is that a higher load current io can be achieved. io also contains less ∆Vout as ripple currents ∆i in each phase are cancelled due to an increase in ripple frequency. This ripple cancellation is due to the interleaving, or parallel connection, of the phases where each phase operate at the same fsw. Yet, the output experiences an effective switching frequency fsw,eff which is a multiple of fsw depending on N, and can thus be expressed as fsw,eff = Nfsw (2.4) where fsw,eff is the effective switching frequency, fsw is the switching frequency of a single phase, and N is the number of phases. Given that fsw can be kept low in each phase, the active power losses (losses occurring during switching) are reduced. Furthermore, the ripple cancellation reduces the requirements for output filtering, reducing the required size of the output capacitance Cout [3, pp. 516-517]. An important aspect of high current applications, such as ASICs, is that transient performance is enhanced. Compared to a single-phase solution, for a given io, each phase’s L is reduced in size as the load is shared among the phases. This reduces the energy storage capabilities of each inductor and thus makes the inductor respond faster to load variations, i.e., transients [3, p. 460]. The operation principle is essentially the same as for the single-phase buck converter and can be explained with reference to Figure 2.2. Ts can be divided into three parts: t1, t2 and t3. During t1, switch Q1 is on and R is supplied with Vin as the current path goes through the inductor L1 while the diode d1 is reverse-biased. Switch Q2 is off, and the energy stored in inductor L2 is dissipated to R where the current path loops around L2 and R through diode D2, which is forward-biased. During t2, both Q1 and Q2 are off, and energy stored in L1 and L2 is dissipated to R, with the current path looping through respective diodes d1 and d2 as they are forward-biased. During t3, switch Q2 is on and R is supplied with Vin as the current path goes through L2 while d2 is reverse-biased. Q1 is off, and the energy stored in L1 is dissipated to R where the current path loops around L1 and R through d1, which is forward-biased [3, pp. 516-519]. As for single-phase buck converters, d1 and d2 may be substituted with switches Q for MPBCs. 5 2. Theory Figure 2.2: Schematic of multi-phase buck converter using N=2 phases. 2.1.2 Discrete inductors in MPBCs Discrete inductors (DL) are conventionally used in MPBCs. To implement DLs in a MPBC, the design procedures in [7] can be followed to determine appropriate values. For the selection of a DL, its value is selected based on Vout, Vin (as D depends on it), fsw and maximum allowable ripple current through the inductor IP P . The value of L can be calculated according to [7] as L = Vout (1 − D) fsw · IP P (2.5) where Vout is the output voltage to the load, D is the duty cycle, fsw is the switching frequency for a single phase, and IP P is the maximum allowable ripple current through the inductor which in accordance with [7] can be expressed as IP P = 0.25Imax N (2.6) where IP P is the maximum allowable ripple current through the inductor, Imax is the maximum current to the load and N is the number of phases in the MPBC. By applying (2.6) and (2.5), the equivalent inductance Leq can further be calculated. Leq is the total inductance value present during a transient event. Essentially, during a transient response such as a step load, the PWM signals to the individual phases start overlapping. This causes multiple phases to conduct simultaneously, in essence placing them in parallel by N phases. In this state, the inductance is reduced by an amount by N. Leq for a DL can be calculated as Leq,DL = L N (2.7) where Leq,DL is the combined equivalent inductance for a DL during a transient event, 6 2. Theory L is the inductance value of a single phase during steady-state and N is the number of phases in the MPBC. 2.1.3 Output capacitors in MPBCs Similar to the inductor, [7] can be followed to determine what appropriate capacitor values might be. According to [7], there are several ways to calculate the minimum Cout required to keep the system within the tolerances specified by the tolerated DC and AC ripples present on the output of the MPBC to the load. One way is to consider the DC ripple relating to ∆Vout(DC). This is the steady-state voltage ripple caused by the current ripple through the inductor. Another way is to consider the AC ripples relating to ∆Vout(AC). The AC ripples are transient ripples caused by stepping (increasing) the load or releasing (decreasing) the load. A voltage dip is the result of a step load, as it takes some time for the MPBC to supply the demanded current. Thus, current is drawn from the output capacitors, which results in a voltage dip (undershoot). The opposite occurs for a load release, where excess charge needs to be stored in the capacitors, causing the voltage to rise (overshoot) at the output. Between the DC ripple and AC ripples, the overshoot determines the required Cout [7, p. 15]. The time taken for Vout to stabilize after releasing the load is given by tovershoot = LeqIstep Vout (2.8) where Leq is the equivalent inductance during the transient, Istep is the maximum load step and Vout is the output voltage. In order to calculate the required output capacitance during an overshoot Covershoot the charge during tovershoot needs to be calculated as Qovershoot = 1 2 · tovershootIstep (2.9) where tovershoot is the time taken for Vout to stabilize after releasing the load and Istep is the maximum load step. Covershoot is then given by Covershoot = Qovershoot ∆Vout(AC) + Istep · DCLL (2.10) where Qovershoot is the charge stored by the output capacitors during a load release, ∆Vout(AC) is the allowable transient output voltage ripple in V, Istep is the maximum load step and DCLL is the DC load line (which may be assumed zero). 2.1.4 Coupled inductors The use of MPBCs solves the issue of applications demanding both a high current and a low current ripple, while also rendering an improved transient performance [1]. To reduce the current ripple of MPBCs using conventional inductors, or discrete inductors (DL), the DLs require a large L. This has a poor effect on the current slew rate during transients as di dt reduces meanwhile large voltage spikes are generated [8]. By replacing the DLs in each phase with coupled inductors (CL) this effect may be counteracted [8]. 7 2. Theory CLs are inductors which are coupled together magnetically: the inductors in the setup share a magnetic core by which the flux generated by the individual inductors interact with each other through a common flux path [9]. Due to this coupling, there exists a difference in inductance magnitude between the steady-state and transient states. To quantify this difference, we are considering a figure of merit based on [8]. The figure of merit (FOM) here denotes the ratio of the rate of change of current in the transient state to that in the steady state. This metric allows us to assess how an inductor’s transient performance compares to its steady-state performance. A higher FOM indicates better transient performance, implying a faster rate of current change during transients. According to [6], achieving a higher FOM is possible by Figure 2.3 depicts how CLs can be implemented in a MPBC using three phases. Inductors are connected individually to each phase of the buck converter and all the inductors are magnetically coupled to each other indicated by the dashed lines between the inductors in Figure 2.3. Figure 2.3: CLs in MPBC [4]. The inductor can be represented as a transformer, where Lm represents the magnetizing inductance per phase, and Lk denotes the leakage inductance per phase. In simulations, the inductors L1, Lm and Ls1, Ls2 symbolize ideal transformer couplings, where the sec- ondary sides of the transformers for each phase are connected in series to simulate magnetic coupling between the inductors. This configuration is designed for systems with more than two phases, ensuring proper orientation of magnetic coupling in coupled inductors (CLs). In this orientation, the current flowing through the conducting inductor is opposite in direction to the currents in other mutually coupled phases. Figure 2.4 illustrates these concepts for a two-phase CL configuration. In CL datasheets, Lm may also be referred to 8 2. Theory as open-circuit inductance (OCL). Figure 2.4: CLs as a transformer [4]. According to [6], achieving a higher FOM involves maximizing the Lm/Lk ratio. A higher Lm enhances flux linkage between phases, thereby improving transient performance. Addi- tionally, the duty cycle also influences FOM performance. When the duty cycle approaches 1 Nph , where Nph represents the number of phases, FOM improves [6]. 2.1.4.1 Notch Coupled Inductor The notch coupled inductor (NCL) is a modification of the CL. The main difference be- tween the two is that the NCL has an increased ratio of Lm/Lk. One way in which this is achieved is to reduce the physical size of the leakage plate surrounding the inductor constituting for Lk. This leaves volume for which Lm can be increased. In this way the ratio of Lm/Lk can be increased [6, p. 634]. According to [6, p. 632] there are several benefits of using NCL over CL in an MPBC. One is that an improved ripple cancellation can be achieved which can either improve the transient performance or lower fsw. Moreover, the higher Lm/Lk ratio in NCL leads to a higher FOM, which improves ripple cancellation [10, p. 1]. This benefit can be leveraged to enhance transient response and reduce component size or to lower fsw within the same footprint, thereby achieving higher overall efficiency. By removing the leakage plate, Lk reduces. The remaining volume can then be used to maximize Lm for a given Isat. This approach for an NCL configuration is depicted in Figure 6(c) in [6, p. 635]. Alternative NCL structures are also feasible [6, p. 634]. 2.1.5 Trans-inductor Voltage Regulator The trans-inductor voltage regulator (TLVR) is a relatively novel technology first proposed in 2020. Its origin can be traced to 2007 [10] in which a setup with indirectly coupled inductors are used. The secondary windings are electrically linked between phases which effectively traps the AC-ripple current [11, p. 114]. This type of inductor is called a trans- 9 2. Theory inductor (TL) [2, p. 2005]. An MPBC utilizing TLVR can be described as a modification of a conventional MPBC where the DLs have been switched out to TLs. A TL consists of magnetizing inductances on the primary side Lm and secondary side Ls with respective leakage inductances lumped as Lk. To form a TLVR, the secondary windings of the TLs are tied together, essentially series connecting the Ls of each TL [12, p. 377]. This series connection is terminated in a separate tuning inductor Lc which effectively tunes the ratio between Lm and Lk of the TLVR [2, p. 1]. The combination of N amount of TLs with secondary windings series connected and terminated by Lc forms a TLVR. A two phase representation of a TLVR can be seen in Figure 2.5. Figure 2.5: Simulation model of TLVR as a transformer [10]. As for the use of CLs in MPBCs, the TLVR’s equivalent impedance per phase in steady- state Leq,ph can also be calculated. The coupling coefficient k comprises Lm and Lk. The primary distinction between TLVR and CL lies in their configurations: CLs feature magnetically coupled inductors, whereas TLVRs can be conceptualized as transformers arranged across different phases, with their secondary windings connected in series to couple primary inductors. Specifically, it is the secondary winding current that couples 10 2. Theory the primary inductors within the phases of the TLVR. Another key difference is that in TLVR, Lm is included in the complete equivalent inductance. Therefore, when comparing to DL, the inductance value is divided between Lk and Lm [6]. 2.2 Integrated Circuit The IC used for testing is the LT8627SP from Analog Devices, Inc. (ADI). It is a buck converter operating with an input voltage range of 2.8 V to 18 V and has an operating frequency range of 300 kHz to 4 MHz. The LT8627SP supports a maximum continuous output current of 16 A and enables multiphase operation up to 12 phases [13, p. 1]. 2.2.1 Operation The switching frequency of the LT8627SP is set via the RT pin by connecting a resistor RT between the RT pin and ground (GND). The signal from the RT pin is fed to an oscillator, which provides the turn-on signal for the control MOSFET each cycle. The current through the control MOSFET Id is received from the power supply through the PVIN pin. As Id passes through the inductor, its current increases until it reaches a peak value set by the voltage on the VC pin, determined by an internal error amplifier comparing the OUTS and SET pin voltages. The output current from the inductor is measured and supplied to the OUTS pin, where it applies a voltage. The SET pin acts as a reference voltage, set by connecting a resistor RSET between the SET pin and GND. When the output of the internal error amplifier meets the voltage set by VC, the control MOSFET turns off, and the sync MOSFET turns on. The inductor current falls, and for CCM operation, the cycle repeats as the next switching time period Ts (clock cycle) initiates [13, p. 13]. The LT8627SP operates in three modes: Forced Continuous Mode (FCM), Pulse-Skipping Mode (PSM), and Synchronization Mode (SM). FCM forces the IC to operate in CCM, avoiding Discontinuous Conduction Mode (DCM) and allowing negative current through the inductor at light loads or during large transients, making it suitable for loads requir- ing fast transient responses or with large load variations. PSM does not allow negative inductor current, leading to DCM operation during light loads. SM synchronizes the oscil- lator to an external frequency, which must have a square-wave characteristic, and may be provided by an external clock generator. In SM the IC operates with the characteristics of FCM [13, pp. 11, 17]. 2.2.2 Pins The LT8627SP has 16 unique pins, but not all are relevant for this thesis. The functions of key pins are summarized in Table 2.1. FCM can be achieved by tying the SYNC/MODE pin to the INTVCC pin, leaving the INTVCC pin floating, or connecting the SYNC/MODE pin to an external clock generator to operate in SM. For SM, the INTVCC pin should be decoupled with a low ESR 1 µF MLCC, and RT should be adjusted to set the programmed fsw 20 % lower than the external fsw. The SVIN pin supplies the internal circuitry, requiring a voltage exceeding 700 mV of the SET pin VSET . SVIN can be tied to PVIN, which provides current to internal circuitry and control MOSFET, ensuring a soft start for the IC. SVIN may also be tied to a separate voltage source bypassed through a 1 µF capacitor which improves efficiency [13, pp. 11, 13]. 11 2. Theory The EN/UVLO pin enables switching when the voltage exceeds 1.32 V and causes shut- down below 400 mV, which can be used as a feature or tied to PVIN if not needed. The SET pin sets the reference voltage for Vout, determined by RSET , with CSET improving noise performance and preventing overcharging which in turn may temporarily short the output to GND. CSET should have a value of 1 µF [13, pp. 24-25]. The LT8627SP can use a fast start-up logic which requires a resistive voltage divider to be connected between L and GND, where the midpoint of the resistive voltage divider is tied to PGFB pin. The PGFB voltage must be within 462.5 mV and 537.5 mV for proper function [13, p 11]. Formulas and a table in the datasheet provide resistor values for the voltage divider [13, p. 25]. The VC pin is a control pin that helps stabilize the voltage at the output. Adding a resistor and capacitor in series to the VC pin improves the control capability of the overall IC and aids in faster stabilization of transients. In our case, the values of the resistor and capacitor were chosen through multiple trials in simulations to ensure that the loop bandwidth of all setups is similar for fair testing. Table 2.1: Functions of pins of LT8627SP. LT8627SP Pins Name Description SW Output of switches to inductor. GND Ground connection. PVIN Power VIN. Provides current for internal cir- cuitry and control MOSFET. SVIN Signal VIN. Provides current for internal cir- cuitry and regulator. EN/UVLO Voltage on pin enables switching. INTVCC Internal 3.4V Regulator Bypass Pin. Internal power drivers and control circuits are powered from this voltage. PHMODE Phase shift of clock signal of CLKOUT pin. SET Reference voltage for internal error amplifier. VC Voltage on pin controls peak switch current. OUTS Measures output voltage to adjust VC. PGFB Power Good Feedback. RT Sets switching frequency. PG Power Good. SYNC/MODE Operation mode (CCM/DCM/FCM). CLKOUT Output clock signal for multiphase operation. Phase determined by the state of PHMODE pin. BST Drive voltage for control MOSFET. 12 2. Theory 2.2.3 Multiphase operation Multiphase operation can be achieved by using multiple LT8627SP ICs in parallel to supply a common load. In this setup, the VC pins of each IC should be tied together, sharing a single RC and CC , and the OUTS pins should also be connected together [13, pp. 25-26]. To enable multiphase operation the PHMODE pin is used to determine the phase shift between the phases. For two-phase operation, the PHMODE pin is connected to GND for a 180° phase shift. For three-phase operation, the PHMODE pin is left floating for a 120° phase shift. For four-phase operation, the PHMODE pin is connected to INTVCC or an external supply for a 90° phase shift. For more than five phases, up to a maximum of 12, the PHMODE pin should be connected to different voltage levels [13, pp. 10, 26]. Table 2.2 summarizes the connection types for the PHMODE pin. Table 2.2: Connection types of PHMODE pin for multiphase configuration. Phases Phase shift PHMODE pin connection 2 180° GND. 3 120° Floating. 4 90° INTVCC pin / external supply. 5 - 12 72° - 30° Differing voltages. 2.2.4 System stability System stability for the LT8627SP is influenced by several factors. One factor is the value of the output capacitors; if too low, they may cause loop instability [13, p. 20]. Parasitics such as ESR and ESL may also affect the internal error amplifier by distorting the signal on the OUTS pin, which can be decoupled with a 150 pF capacitor. Components tied between the VC pin and GND, specifically a resistor RC and capacitor CC , are part of the control loop which directly influences system stability. This loop consists of a modulator, the MOSFETs and inductor, and CC . The modulator, MOSFETs and inductor generates a current determined by the voltage on the VC pin. The output capacitors integrates this current and CC integrates the output current of the internal error amplifier to which the output current is fed to. This results in two poles in the control loop, with a zero being provided by RC [13, p. 22]. 2.3 Simulation software The primary simulation software used is LTSpice [14]. This tool allows simulation of cir- cuits and measurement of various parameters, such as output voltage, load step response, total harmonic distortion (THD), and loop stability. IC manufacturers may provide simu- lation files for their ICs in LTSpice. Simulation and measurement results may differ due to non-ideal behaviors, such as the DC-bias characteristic of multi-layer ceramic capacitors (MLCCs), which reduces their capacitance values under certain voltages and temperatures. 13 2. Theory 14 3 Case setup This section will detail the necessary information for setting up simulations and test config- urations. Simulation details will include the selection of IC parameter values, the process of constructing IC and inductor models, and steps taken to develop simulation models. Test setup specifics will cover aspects such as inductor configuration, board modifications, simulation setup, and parameters considered during testing. 3.1 Testboard The testboard provided by ADI is a six-phase MPBC using the LT8627SP as the buck- converter IC for each phase. Three test boards in total were supplied by ADI as back- up but also for convenience as to mount different inductor types on the boards. The only parameter aimed to be changed between different measurements are the inductors themselves. Thus the intention is for the remainder of the board to remain unchanged as for standardisation between tests unless otherwise specified. One of the testboards without inductors mounted can be seen in Figure 3.2. As described in section 2.2.3 the PHMODE pin should be connected to differing voltage levels to realize a six-phase operation. However, for the board this is not the case. The PHMODE pin of each phase is connected to GND. As seen in Table 2.2 this means a 180◦ phase shift between the ICs. Despite appearing so, this does not mean the MPBC is operating as a two-phase setup. There is a six-phase operation consisting of three parallel two-phase operations. Due to the layout this means that the following phase configurations are operating with a phase shift of 180◦ to each other: PH1 and PH4, PH2 and PH5, PH3 and PH6; where PH1 through PH6 correspond to the first through the sixth phase. Despite these phase pairs switching with a D of 0.5 with respect to each other they are still operating within a common Ts. Hence each phase’s maximum on-time results in (2.3) remaining true with D being less than or equal to 1 6 . The phase configuration can be seen in the SYNC voltages of each phase as illustrated in Figure 3.1 where the colored text represent the two-phase pairs. 15 3. Case setup Figure 3.1: Simulated SYNC voltage distribution. The SYNC voltages in turn are driven by an external clock-circuit consisting of the IC LTC6909. It is an oscillator capable of providing up to eight synchronized outputs and thus able to provide the SYNC signals for the six-phase setup on board. It operates with a supply voltage between 2.7 V and 5.5 V. The output frequency is set by a resistor connected to the SET pin of the LTC6909 RSET,LT C and its value can be calculated according to [15, p. 1] with fOUT = 20MHz · 10k RSET,LT C · N (3.1) where fOUT is the output frequency of the LTC6909, RSET,LT C is the SET resistor for LTC6909, and N is the number of outputs being driven by the IC. As a 16.5 kΩ resistor is tied to the SET pin of the LTC6909 on the testboard (3.1) gives fOUT a value of 2.02 MHz with this resistor size. Considering the resistor’s tolerance of ±1 % this gives fOUT a range between 2.00 MHz and 2.04 MHz. 16 3. Case setup Figure 3.2: Testboard provided by ADI. 3.1.1 Modifications Despite attempting to mimic the testboards, some adjustments are made in order to ease performing simulations. For multiphase operation, the VC pins of all phases should be tied together and share a single RC and CC as mentioned in section 2.2.3. In the schematic of the testboard this is done, but in the implementation on the board RC and CC are only tied to PH1. Therefore RC and CC are tied to PH1 as well. According to the schematic, the values for RC and CC on the board are 348 Ω and 1000 pF respectively with a capacitor sized 10 pF placed in parallel. In reality, these are not placed, since the schematic was for a different set of inductors. For our application we had to find a suitable RC and CC which we got after some trial and error in the simulations. After performing stability measurements with different values for RC and CC , their values were chosen to 10 Ω and 10 000 pF respectively. 3.2 Simulation setup For simulations the software LTspice will be used. Different configurations of MPBCs will be constructed within the software, meaning different inductor topologies will be integrated with the MPBCs being: DL, CL and TLVR. The simulations were carried out with the IC LT8627SP. The simulations were intended to be comparable between each other and to the testboards. This means constructing simulation models which resemble the testboards as closely as possible with the only difference between simulations being the inductor used; yet the equivalent inductance should remain the same. The major parameters which remain the same such as Vin and fsw are summarized in Table 3.1. 17 3. Case setup Table 3.1: Main parameters to be used in simulations. Parameter Value Unit Description Vin 12 V Input voltage. Vout 1 V Output voltage. fsw 2 MHz Switching frequency. N 6 Phase count. Istep 60 A Maximum load step. di dt 120 A µs−1 Transient step size. 3.2.1 Investigation parameters The simulation tests to be performed contain a number of variables. One variable is loop bandwidth and stability of the configuration. Another is step-load response, meaning how the system responds to sharp transients. This entails a number of phenomena: how ∆Vout is affected and if it remains within acceptable levels, whether the switch voltage between the output of the MOSFETs and input of the inductors overlaps between phases. Furthermore, power supply rejection ratio (PSRR) will be investigated. This means that if noise is present from the Power source, how much voltage variation would be present at the output. Additionally different Vin/Vout ratios will be investigated to see how the above mentioned variables behave in response to a change in this ratio. A final variable is the efficiency where different Vin/Vout ratios will be compared between different inductor topologies for MPBCs where an efficiency comparison will be done by comparing the power received to the circuit and power supplied to the load. 3.2.2 Differences between simulations and testboard The value of CSET . When running simulations with the value of 1 µF being mounted on board the simulations significantly slowed down. Namely, a long simulation time was required for Vout to reach its intended level. Therefore, for simulations, CSET is given a value of 10 pF for a fast rise of VSET . Other resistors and capacitors which are not described further in this section are ideal. These are for instance the RT resistor and INTVCC capacitor. Further, there are ideal voltage sources placed in the simulation models with 0 V and no series resistance. These are used for current measurement. The primary voltage source supplying VIN is also an ideal voltage source. 3.2.3 Inductors Provided by Ericsson is a component library including custom inductor models which exhibit non-ideal characteristics and can be implemented into LTspice. While unclear exactly what type of non-ideal characteristics that are present for the components, they may still be considered as more realistic models than ideal parameters. However, no inductors are chosen from the component library. For DL the reason is that selecting inductors from the component library results in large, irregular spikes in the output voltage which are deemed non-realistic. The inductors chosen are however modeled to an extent after the DL used on board. They have an ESR of 0.22 mΩ which is close to its nominal 18 3. Case setup value of 0.29 mΩ and the DLs have a value of 100 nH. In reference to section 2.1.2 equations (2.6) and (2.5) can be used to determine whether a value of 100 nH is appropriate. For (2.5) Vout and fsw are simply applied from Table 3.1. D is calculated according to (2.1) as 1 12 with values of Vout and Vin in Table 3.1. IP P is taken as 25 % of maximum current per phase in accordance with [7, pp. 10-11]. Applying (2.6) using Imax of 90 A from the load profile in Figure 4.3 gives IP P a value of 3.75 A, which applied to (2.5) gives L a value of 122 nH. This value is 22 % larger than the chosen value for DL, hence the chosen value for DL might not be optimal, due to the size constraint and availability, 100 nH was chosen. The models for CL, NCL, and TLVR are not part of the standard simulation library. Therefore, equivalent models were created based on the guidelines provided in [10], which detail various inductor models and their differences. A critical aspect when modeling inductors in simulations is ensuring that all inductors are oriented in the same direction [16]. Figure 3.3: Two Phase CL. Figure 3.3 illustrates two phases of the six-phase model made in simulation. The entire model is found in Appendix A in Figure A.6. In Figure 3.3, Lm is 300 nH, and Lk is 100 nH, derived from the datasheet of the CL1208-6-100TR-R inductor used in the experimental setup, where the open circuit inductance is 400 nH and the short circuit inductance is 100 nH. Considering these, Lm can be calculated as Lm = opencircuitinductance − shortcircuitinductance = 300 nH (3.2) The ESR is set at 0.1 mΩ per phase, distributed uniformly across all inductors, resulting in an ESR per phase of 0.1 mΩ. The coupling factor k for CL typically reaches 0.95 [17]. In contrast, NCL achieves a higher Lm/Lk ratio compared to CL [6], maintaining Lk at 100 nH while increasing Lm to 2000 nH. For TLVR, the overall inductance value is the sum of Lk and Lm, where the 100 nH total is divided between Lm (70 nH) and Lk (30 nH). However, the structure of both NCL and TLVR remains the same as CL for simulations [10]. 19 3. Case setup 3.2.4 Output Capacitance Another deviation from the testboards are the output capacitors used in simulation. For one, they are lumped together on the output between the MPBC and the load. For sim- ulation purposes this should have little to no impact as opposed to placing the capacitors in exact accordance with the schematic as Vout. For the other, custom capacitor models are used from Ericsson’s component library. The capacitors chosen from this library are intended to be as close as possible to what is mounted on the board. The capacitor values and tolerances have been prioritized, where other characteristics such as package size and max temperature are less prioritized. One electrolytic capacitor and six different MLCCs are chosen in total. These are listed in Table 3.2 with a total nominal capacitance value of 4430.7 µF consisting of 75 capacitors. In Table 3.2 the capacitor EEFHX0D561R4 is an electrolytic capacitor while the remainder are MLCCs. Table 3.2: Chosen output capacitors for simulation. Capacitor Value [µF] Amount Total [µF] EEFSX0D561E4 560 6 3900 GRM32ER71E226ME15 22 12 264 GRM21BR60J226ME39 22 36 792 GRM21BR71H105KA12 1 8 8 GRM033C80J105ME05 1 6 6 GRM1555R71H104KE14 0.1 6 0.6 GRM188R71H104KA93 0.1 1 0.1 In reference to section 2.1.3 the steps in calculating Covershoot can be followed to determine whether a Cout of 4430.7 µF is sufficient or not. Applying (2.8) with Leq of 20.33 nH for DL, Vout of 1 V and Istep of 60 A according to Table 3.1 gives tovershoot a value of 1.22 µs. With this value, (2.9) gives Qovershoot a value of 36.6 µC. Applying (2.10) and assuming a strict value for ∆Vout(AC) of ±2 % gives Covershoot a value of 1830 µF. The different capacitance values are summarized in Table 3.2. The chosen value for Cout of 4430.7 µF is 242 % greater than the calculated Covershoot. Hence a Cout of 4430.7 µF should suffice to keep ∆Vout(AC) within ±2 %. Furthermore, it should not cause loop instability as described in section 2.2.4. 3.3 Lab setup This section aims to describe the equipment used for measuring different variables of interest, presenting these variables, describe the test board. 3.3.1 Equipment To perform measurements on the board different types of equipment were required. The equipment used is summarized in Table 3.3. 20 3. Case setup Table 3.3: Equipment used for measurements. Part Name Manufacturer Power supply SM70-45D Delta Elektronika Clock circuit power supply SM70-AR-24 Delta Elektronika Electronic load Chroma 6312A Chroma Oscilloscope HD4096 Teledyne Lecroy Stability analyzer Bode 100 OMICRON Lab Injection Transformer B-WIT 100 OMICRON Lab Multimeter TX3 Tektronix 3.3.2 Adjustments Some adjustments had to be made to the board in order to perform certain measurements. One adjustment that was made was to let the OUTS pins of each IC share a common resistor. Prior to this adjustment each IC had a 100 Ω resistor tied between its OUTS pin and the common Vout. After adjustment, the 100 Ω resistors were removed from each phase and resistors were mounted in parallel between the OUTS pin of each phase and a common point connected to a Bode test point. To illustrate the change With reference to Figure 3.5, R125 through R130 were connected with steel wires, i.e. between the pads in row 3 and row 4. Essentially this connects all OUTS with the measurement point labeled BODE TEST B. This however assumes there is a connection between the pads in row 1 and row 2. A single resistor was mounted between two pads in row 2 and row 2 sized 10 Ω. Figure 3.4: Disturbance injection setup The figure 3.4 shows the connection made where the E53 and E54 are the injection points which is across the 10 Ω resistor. The disturbance is given by an instrument namely Bode 100 which can inject the disturbance of a frequency sweep across the resistor and receive the response of the setup giving a bode plot through the UI when connected to 21 3. Case setup the computer. Figure 3.5: Part of the board dedicated to Bode measurement. The picture in figure 3.5 shows the place at which the above-mentioned connection was made. 22 4 Implementation 4.1 LT8627SP This section will cover the implementation of the LT8627SP and its use with DL, NCL, CL and TLVR as a six-phase configuration. 4.1.1 General simulation model The general simulation model is based on the board as already described in section 3.2. The configuration can be seen in Figure 4.1 where Figure 4.1a depicts the first phase and Figure 4.1b depicts the third phase. The remaining phases are identical to phase 3. The load is shared between the converters where the point of connection lies past each phase’s power inductor as seen by the A connection. Between the load and A lies the lumped output capacitors. The simulation model can be seen in its entirety in Appendix A. (a) (b) Figure 4.1: General six-phase configuration of LT8627SP showing (a) the first phase and (b) third phase. . 4.1.2 Stability analysis For the stability analysis, a frequency response analyzer (FRA) was employed to assess the circuit’s frequency response. The FRA was inserted in place of the resistor connected to the OUTS1 of the first phase, with the OUTS pins of all other buck converters connected, placing the FRA in series between the OUTS pins of all buck converters and the output voltage. The FRA operates by introducing a disturbance into the circuit—a frequency 23 4. Implementation sweep across the specified range—and plots a Bode plot by analyzing the ratio of Vin to Vout. The parameters for the FRA analysis are shown in Figure 4.2. Figure 4.2: FRA parameters. The disturbance range was set from 10 kHz to 1 MHz to test a wide frequency spectrum and observe the gain at each disturbance frequency. Additionally, the phase change at each frequency was monitored, as it impacts stability. The analysis commenced at 80 µs to allow the circuit to stabilize, and each frequency disturbance was analyzed for 10 µs. The parameters pp0 and pp1 refer to the amplitude of the disturbance voltage, typically prescribed to be less than 1 % of the output voltage. Hence, a disturbance voltage of 0.005 V was used, considering the output voltage is 1 V. This will be the first test done to see what values of resistor and capacitor is needed at the Vc to make the circuit stable for the operation with the respective inductor setup. 4.1.3 Efficiency Efficiency simulations were conducted under two scenarios to allow for comprehensive comparison. In the first scenario, a load profile of 19.92 A was used, and the circuit’s 24 4. Implementation efficiency was tested with a voltage sweep. The voltage was incrementally adjusted, al- lowing sufficient time for parameter stabilization, and the RMS values of input voltage, input current, output voltage, and output current were recorded to calculate efficiency. Efficiency readings at various points were plotted for analysis. In the second scenario, a constant input voltage of 12V was applied, followed by a current sweep. The load demanded each current value for 100 µs to ensure steady-state conditions before taking the necessary readings. 4.1.4 Step load response The step load response test utilized the load profile depicted in Figure 4.3. An input voltage of 12 V was applied, and the response was monitored in terms of output voltage ripple and rate of change of current. The load profile involved a load step from 30 A to a constant 90 A, followed by a load release back to a constant 30 A. This profile simulated four states for the multi-phase buck converters (MPBCs): low-load steady-state, transient load step, high-load steady-state, and transient load release. The transient steps occurred over 500 ns, yielding a di dt of 120 A µs−1. The steady-state conditions were maintained long enough for oscillations to stabilize, with low-load steady-states simulated for 50 µs and high-load steady-state for 99 µs. The total simulation time was 350 µs, with data collection commencing at 150 µs to ensure stability. Figure 4.3: Simulation load profile. 4.1.5 Power system rejection To evaluate the effect of input power variations on different inductor setups, an FRA was used in series with the input supply. The FRA generated a sinusoidal disturbance through a frequency sweep, allowing the observation of how this disturbance impacted the output. The FRA parameters are shown in Figure 4.4 25 4. Implementation Figure 4.4: FRA of PSRR parameters The frequency sweep ranged from 100 Hz to 1 MHz, with a disturbance amplitude of 0.12 V. Each frequency was analyzed for 1 ms to ensure comprehensive evaluation. 4.2 Building & testing physical model This section details the implementation of the physical test board. 4.2.1 Stability analysis Stability measurements were performed with the modification described in section 3.3.2. A Bode 100 was connected to an injection transformer supplying a disturbance signal to the board, with the receiver connected to the Bode 100 to analyze the output voltage from the converters. A frequency sweep from 10 kHz to 3 MHz was applied with a source level of -19 dBm. A 20 dB attenuator was used due to the sensitivity of the buck converter, and an internal attenuation of 10 dB was configured in the Bode 100 UI. The receiver’s bandwidth was set to 100 Hz to obtain a noise-free reading. 26 4. Implementation 4.2.2 Efficiency Efficiency tests were conducted under two scenarios: 1. Voltage sweep with a constant 20 A load. 2. Current sweep with a constant 6 V input voltage. Voltage and current were varied, and at each variation, the RMS values of input voltage, input current, output voltage, and output current were recorded to calculate and plot the efficiency curve. 4.2.3 Voltage ripple Voltage ripple measurements were taken under various conditions to observe the ripple variations with different voltage and current settings. An oscilloscope was used to measure the ripples for different input voltages and currents, comparing the variations between CL and DL configurations. 27 4. Implementation 28 5 Results This section presents and discusses the results from both simulations and laboratory test- ing. Initially, simulation results are showcased, including tests performed for DL, NCL, TLVR and CL. Subsequently, results from the laboratory experiments involving DL and NCL are presented. 5.1 Simulations 5.1.1 Stability Response The first test done was the stability response of the circuit with different configurations of the inductors. For the DL and CL configuration the value of RC and CC was chosen as 10 Ω and 10 nF respectively, With that the loop bandwidth for CL is 90.9 kHz and the phase margin for CL is 51.4◦. For DL the loop bandwidth is 89.7 kHz and the phase margin is 53.40◦. For TLVR we had to choose different values of RC and CC . The values of 50 Ω and 14 nF were chosen where we got the loop bandwidth of 76.1 kHz and the phase margin of 58.2◦. And lastly for NCL the values of 0.1 Ω and 2 nF were chosen for RC and CC where we got the loop bandwidth of 86.2 kHz and the phase margin of 3.9◦. Figure 5.1 shows the bode plots we obtained in the simulations of all four configurations. 29 5. Results (a) DL (b) CL (c) NCL (d) TLVR Figure 5.1: Bode plots from FRA Analyser 30 5. Results 5.1.2 Step Response Figure 5.2 illustrates the phase inductor currents during a steady-state load of 30 A. DL and CL exhibit similar characteristics; however, the current ripple through CL is signifi- cantly lower than that through DL. Specifically, the current ripple in CL is approximately 1.2 A, whereas for DL, it is around 4.8 A. This indicates that the current ripple in DL is 400 % higher than in CL. This discrepancy is expected because CLs are magnetically coupled, allowing for a more uniform distribution of current ripple, unlike DLs. This trend is also evident in NCL, where the current ripple is about 0.6 A for the inductor in PH4 (IL4 in Figure 5.2c). The current ripple in NCL is 50 % lower than in CL and only 12.5 % of that in DL, highlighting the significant impact of higher magnetizing inductance on reducing output current ripple. Additionally, the current ripples in NCL occur at a higher frequency. In any given phase, roughly five cycles of inductor charge and discharge occur for NCL compared to DL, CL, or TLVR. This higher frequency may reduce the re- quirement for output capacitance but could introduce higher-order harmonics. For TLVR, the magnetic coupling influences each phase’s current such that when one phase’s current decreases and another’s increases, a small increase in the current of the falling phase is observed. However, the overall current ripple is around 5.6 A for any phase, similar to DL due to the design of TLVR, where the total inductance is split between magnetizing and leakage inductance, unlike CL and NCL. (a) DL (b) CL (c) NCL (d) TLVR Figure 5.2: Phase inductor currents during 30A load. Figure 5.3 shows the phase inductor currents during a steady-state load of 90 A. The analysis is similar to that of Figure 5.2, with the approximate current ripple being 5 A for DL, 1.2 A for CL, 0.7 A for NCL, and 6 A for TLVR. A noteworthy observation at the higher load of 90 A is the presence of distortions across all inductor topologies. These distortions are most apparent in CL, where dips and overshoots are seen at the respective bottom and top peaks of the current. The most severe distortion is observed in NCL (Figure 5.3c), where the inductor current waveforms show variations in the magnitude of current ripple, with rounded peaks. There seems to be no consistent pattern to these distortions. Additionally, as seen in Figures 5.2c and 5.3c, there is almost no phase difference between the currents of each phase. This is attributable to the high Lm in NCL, which ensures 31 5. Results even current distribution between phases. The high Lm results in significant flux linkage between the phases, contributing to the observed even current distribution. (a) DL (b) CL (c) NCL (d) TLVR Figure 5.3: Phase inductor currents during 90A load. Figure 5.4 displays the load profile and combined inductor currents. The figure also high- lights the upper and lower margins needed to calculate the current slew rates of the load step and load release. The lowest current overshoot occurs in CL with 114.0 A, confirming its previously noted lowest current ripple in Figures 5.2 and 5.3. However, CL exhibits the worst current undershoot, reaching −46.9 A, while other inductor topologies remain above 0 A. Despite this, CL seems to stabilize faster and with less ringing than the other inductors. The waveforms of DL and NCL are similar in both ripple and overshoot/un- dershoot characteristics, with NCL showing slightly smaller undershoot. It is noted that the overshoot and undershoot are influenced by the high capacitance on the output side, which can be controlled by adjusting the capacitors. (a) DL (b) CL (c) NCL (d) TLVR Figure 5.4: Load profile and combined inductor currents. 32 5. Results Figure 5.5 provides a closer view of the load profile and combined inductor currents during the load step. Marked in each subfigure are the current values and times at which the com- bined inductor currents cross the margins. By considering the 10 % and 90 % thresholds, di dt during the load step can be calculated with di dt = i90 − i10 t90 − t10 (5.1) where di dt is the current slew rate through the inductor, i90 is the current value at 90 % of the final value, i10 is the current value at 10 % of the final value, t90 is the time at 90 % of the final value, and t10 is the time at 10 % of the final value. These values, taken from the subfigures in Figure 5.5 and applied to equation (5.1), yield the di dt during the load step for each inductor topology, presented in Table 5.1. The fastest response is observed in DL at 19.05 A µs−1 while the slowest is in TLVR at 15.24 A µs−1. Table 5.1: Calculated di dt during load step. Inductor di dt [A µs−1] DL 19.05 CL 18.92 NCL 18.56 TLVR 15.24 (a) DL (b) CL (c) NCL (d) TLVR Figure 5.5: Load profile and combined inductor currents during load step. Figure 5.6 shows a closer view of the load profile and combined inductor currents during the load release. Using the same analysis as for the load step, the di dt during the load release is calculated with (5.1) for each inductor topology, with results presented in Table 5.2. Negative values indicate a falling current. These values differ from the trend observed during the load step. Notably, DL still exhibits the fastest response at −19.59 A µs−1. While most inductor topologies show similar rising and falling di dt , NCL is an outlier, being 33 5. Results slower during the load release with −12.51 A µs−1 compared to its load step performance of 18.56 A µs−1. Table 5.2: Calculated di dt during load release. Inductor di dt [A µs−1] DL -19.59 CL -12.51 NCL -18.61 TLVR -15.12 (a) DL (b) CL (c) NCL (d) TLVR Figure 5.6: Load profile and combined inductor currents during load release. Figure 5.7 illustrates the voltage drop at the onset of an increase in current demand. In DL, the voltage drop and subsequent rise are more pronounced compared to the other configurations, with a drop to just under 0.96 V and an overshoot reaching 1.02 V. For CL, the voltage drop is slightly above 0.96 V, with an overshoot marginally below 1.01 V. NCL exhibits a similar voltage drop to DL at 0.96 V but with a smaller overshoot of 1.01 V. TLVR outperforms DL in this scenario, with a voltage drop slightly exceeding 0.96 V and an overshoot slightly below 1.01 V. It is noteworthy that TLVR has the highest voltage ripple amplitude, while CL exhibits the lowest. 34 5. Results (a) DL (b) CL (c) NCL (d) TLVR Figure 5.7: VOUT during load step. Figure 5.8 shows the voltage overshoot during the load release. Similar patterns are observed as in Figure 5.7 for the load step. The waveforms for DL and NCL are similar in response to the load release, appearing as inverses of the load step waveforms. DL exhibits the highest overshoot at 1.042 V. However, for CL, the overshoot during the load release is sustained, and the undershoot followed by the overshoot is sharper and greater in magnitude compared to the other inductor topologies, reaching a minimum of 0.94 V. (a) DL (b) CL (c) NCL (d) TLVR Figure 5.8: VOUT during load release. Figure 5.9 depicts VSW for each phase during the load step. The load step is initiated at 200 µs, and its effect is visible around 200.5 µs onwards, where the VSW for each phase is active for longer durations than before the load step. This indicates proper functioning, as longer on-time means more power is supplied to the load. Additionally, no overlapping of VSW signals occurs, signifying that each phase is switching independently. 35 5. Results Figure 5.9: Phase VSW during load step. Figure 5.10 depicts each phase’s VSW during the two steady-state loads. Although difficult to discern, any VSW in 5.10b has a longer on-time compared to Figure 5.10a, corroborating the prior analysis regarding Figure 5.9. (a) 30A (b) 90A Figure 5.10: Phase VSW during steady-state load. 5.1.3 Efficiency Figure 5.11 shows the efficiency of different inductor setups during a voltage sweep, keeping the load constant. From the figure, we can see that the efficiency of CL and NCL is almost the same, in the same way, the efficiency of DL and TLVR is almost the same, but 36 5. Results comparing all the cases the efficiency of the CL and NCL setups are higher compared to DL and TLVR. In all cases the efficiency decreases with an increase in voltage, this might be because of the LT8627’s internal voltage divider which is present in the chip to supply 3.5 V to the internal excitation in the chip. We tested the same in the hardware where we got similar efficiencies. One thing to note is that the CL and NCL efficiencies rise near the 6 V mark, this is because of the notching effect which is mentioned in 2.1.4. (a) DL (b) CL (c) NCL (d) TLVR Figure 5.11: Efficiency with 20 A constant load. Figure 5.12 shows the efficiencies with current sweep with a constant input voltage of 12 V. For CL and NCL the efficiency slope is a decreasing slope the max efficiency reaching 69 %, whereas the efficiency of DL and TLVR increases in the first step after which there is a decreasing slope with the maximum efficiency of 68 %. Comparing all cases, the efficiency of CL and NCL is slightly higher and the trend of efficiencies can be comparable to the results in 5.2.2 37 5. Results (a) DL (b) CL (c) NCL (d) TLVR Figure 5.12: Efficiency with varying load with 12 V supply. 5.1.4 Power system rejection ratio In Figure 5.13, we examine the gain with respect to Vout/Vin ratio using FFT analysis. The DL configuration shows a maximum gain reaching up to 50 dB, whereas the gain with CL peaks at 0 dB. This indicates that the DL circuit is more susceptible to transmitting noise, while the CL circuit is more effective at rejecting the noise supplied. (a) DL (b) CL Figure 5.13: PSRR plots of DL and CL 38 5. Results 5.2 Lab 5.2.1 Stability measurement Figure 5.14 presents the Bode plots acquired from the physical setup for both CL and DL configurations. The chosen values for RC and CC were 10 Ω and 10 nF, respectively. The loop bandwidth for CL was observed to be 79.9 kHz, with a phase margin of 44.3◦. In contrast, the loop bandwidth for DL was 73.8 kHz, and the phase margin was 39.2◦. (a) DL (b) CL Figure 5.14: Measured Bode plots of DL and CL 5.2.2 Efficiency The measured efficiencies align with the trends observed in Section 5.1.3. Figure 5.15 illustrates the efficiency of the circuit with a 6 V input voltage, showing that CL achieves a higher maximum efficiency (87 %) compared to DL (86 %). 39 5. Results (a) DL (b) CL Figure 5.15: Efficiency for varying load with 6V supply. Figure 5.16 demonstrates the efficiencies of CL and DL when subjected to a voltage sweep with a constant load of 19.94 A. Again, CL shows higher efficiency with a maximum of 89 %, whereas DL peaks at 87 %. (a) DL (b) CL Figure 5.16: Efficiency for varying voltage with constant 20 A load. 5.2.3 Voltage Ripple Output voltage ripples were tested under multiple conditions, and it was observed that the voltage ripple amplitude remained constant. Figure 5.17, although not clear in de- tail, shows the output ripples measured using an oscilloscope. While the peak-to-peak amplitude of the ripples is approximately 3 mV for both CL and DL, there is a notable difference in their shapes. One more thing to mention is that the voltage ripple in DL has ripples with low frequencies and High frequencies whereas the voltage ripples from CL has ripples only of high frequencies. This can be taken into consideration as if used in radio applications it may effect the radio signals. 40 5. Results (a) 12V 0A DL (b) 12V 60A DL (c) 12V 0A CL (d) 12V 60A CL Figure 5.17: Measured Voltage Ripple 41 5. Results 42 6 Conclusion From the simulation results, it can be concluded that NCL and CL exhibit comparable efficiency. Additionally, they demonstrate higher efficiency than both DL and TLVR across most duty cycles, as indicated by the input voltage sweep simulation with efficiencies of CL and NCL at 95 % compared to 91 % for DL and TLVR at 6 V. For lower loads, CL and NCL outperform DL and TLVR, having efficiencies of 69 % compared to 64 % for a load of 20 A. At higher loads, the performance is similar, albeit slightly higher for CL and NCL in the 90 A case, with efficiencies of 68 % compared to 67 % for DL and TLVR. These efficiency trends observed in simulations are corroborated by hardware implementation results, further demonstrating the influence of inductor configuration on efficiency and voltage ripple. The implications of these findings extend to the sustainability and ethical impact of power electronics design. The enhanced efficiency observed in CL and NCL configurations leads to reduced power consumption and thermal stress, resulting in lower energy costs and a diminished carbon footprint, crucial for environmental sustainability. In terms of current slew rate, DL achieves the highest with 19.05 A µs−1, while TLVR has the lowest with 15.24 A µs−1 during the load step. For the load release, DL again proves to be the fastest at −19.59 A µs−1, whereas NCL is the slowest at −12.51 A µs−1. CL exhibits better performance regarding the magnitude of current overshoot, achieving the lowest at 114.0 A during the load step and an improved return to steady-state. However, CL’s performance during the load release is less favorable, reaching −46.9 A. When evaluating the output voltage drop from load steps and releases, all inductor topologies show similar behavior, with the voltage dropping to 0.96V and the recovery voltage overshoot having a maximum magnitude of 1.01V. Overall, the comparative analysis of DL, CL, NCL, and TLVR highlights the advantages of CL and NCL in achieving higher efficiency and improved noise rejection capabilities. This analysis provides a foundational understanding that can guide the design and optimization of power converters towards more sustainable and reliable electronic systems. 43 6. Conclusion 44 Bibliography [1] J. Gallagher, “Coupled Inductors improve multi phase buck efficiency,” Pulse Elec- tronics, 2006. [Online]. Available: https : / / www . pulseelectronics . com / wp - content/uploads/2021/01/Pulse- Power- BU- Coupled- Inductors- Improve- Buck-Efficiency.pdf. [2] H. Shao, T. Zhao, D. Fu, D. Huang, and J. Zhou, “Analytic model and design procedure of the single-secondary trans-inductor voltage regulator,” in 2021 IEEE Energy Conversion Congress and Exposition (ECCE), 2021, pp. 2005–2010. doi: 10.1109/ECCE47101.2021.9595952. [3] M. H. Rashid, Power Electronics Handbook (4th Edition). Elsevier, 2018. [Online]. Available: https : / / app . knovel . com / hotlink / toc / id : kpPEHE000C / power - electronics-handbook/power-electronics-handbook. [4] A. Ikriannikov and T. Schmid, “Magnetically coupled buck converters,” in 2013 IEEE Energy Conversion Congress and Exposition, 2013, pp. 4948–4954. doi: 10. 1109/ECCE.2013.6647368. [5] S. Sander, “An introduction to Transformer-Inductor Voltage Regulators (TLVR),” Ericsson, Tech. Rep., 2022, unpublished. [6] A. Ikriannikov and D. Yao, “Converters with Multiphase Magnetics: TLVR vs CL and the Novel Optimized Structure,” in PCIM Europe 2023; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2023, pp. 1–10. doi: 10.30420/566091088. [7] C. Parisi, “Multiphase Buck Design From Start to Finish (Part 1),” Texas Instru- ments, Inc., 2021. [Online]. Available: https://www.ti.com/lit/an/slva882b/ slva882b.pdf?ts=1659274643749. [8] F. Zhu and Q. Li, “Coupled inductors with an adaptive coupling coefficient for multiphase voltage regulators,” IEEE Transactions on Power Electronics, vol. 38, no. 1, pp. 739–749, 2023. doi: 10.1109/TPEL.2022.3203855. [9] P.-L. Wong, P. Xu, P. Yang, and F. Lee, “Performance improvements of interleaving vrms with coupling inductors,” IEEE Transactions on Power Electronics, vol. 16, no. 4, pp. 499–507, 2001. doi: 10.1109/63.931059. [10] A. Ikriannikov, “Multiphase designs, decisions, and trade-offs with trans-inductor voltage regulators,” Analog Devices, Inc., 2023. [Online]. Available: https://www. analog.com/en/technical-articles/multiphase-designs-decisions-trade- offs-trans-inductor-voltage-regulators.html. [11] M. Xu, Y. Ying, Q. Li, and F. C. Lee, “Novel coupled-inductor multi-phase vrs,” in APEC 07 - Twenty-Second Annual IEEE Applied Power Electronics Conference and Exposition, 2007, pp. 113–119. doi: 10.1109/APEX.2007.357503. [12] S. Krishnamurthy, D. Wiest, and Y. Zhou, “Trans-inductor voltage regulator (tlvr): Circuit operation, power magnetic construction, efficiency and cost trade-offs,” in 45 https://www.pulseelectronics.com/wp-content/uploads/2021/01/Pulse-Power-BU-Coupled-Inductors-Improve-Buck-Efficiency.pdf https://www.pulseelectronics.com/wp-content/uploads/2021/01/Pulse-Power-BU-Coupled-Inductors-Improve-Buck-Efficiency.pdf https://www.pulseelectronics.com/wp-content/uploads/2021/01/Pulse-Power-BU-Coupled-Inductors-Improve-Buck-Efficiency.pdf https://doi.org/10.1109/ECCE47101.2021.9595952 https://app.knovel.com/hotlink/toc/id:kpPEHE000C/power-electronics-handbook/power-electronics-handbook https://app.knovel.com/hotlink/toc/id:kpPEHE000C/power-electronics-handbook/power-electronics-handbook https://doi.org/10.1109/ECCE.2013.6647368 https://doi.org/10.1109/ECCE.2013.6647368 https://doi.org/10.30420/566091088 https://www.ti.com/lit/an/slva882b/slva882b.pdf?ts=1659274643749 https://www.ti.com/lit/an/slva882b/slva882b.pdf?ts=1659274643749 https://doi.org/10.1109/TPEL.2022.3203855 https://doi.org/10.1109/63.931059 https://www.analog.com/en/technical-articles/multiphase-designs-decisions-trade-offs-trans-inductor-voltage-regulators.html https://www.analog.com/en/technical-articles/multiphase-designs-decisions-trade-offs-trans-inductor-voltage-regulators.html https://www.analog.com/en/technical-articles/multiphase-designs-decisions-trade-offs-trans-inductor-voltage-regulators.html https://doi.org/10.1109/APEX.2007.357503 Bibliography PCIM Europe 2022; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2022, pp. 1–6. doi: 10.30420/565822053. [13] Analog Devices, Inc., LT8627SP 18V/16A Step-Down Silent Switcher 3 with Ul- tralow Noise Reference, Accessed: Jun. 05, 2024. [Online]. Available: https://www. analog.com/media/en/technical-documentation/data-sheets/lt8627sp.pdf. [14] LTSpice. (17.1.15). Analog Devices. Inc. [15] LTC6909 1 to 8 Output, Multiphase Silicon Oscillator with Spread Spectrum Mod- ulation, LT 0111 REV A, Linear Technology Corporation, 2009. [Online]. Avail- able: https://www.analog.com/media/en/technical- documentation/data- sheets/6909fa.pdf. [16] Eton, CL1208 Multi-phase power inductors, Accessed: May. 30, 2024, Cleveland, OH, USA, 2019. [Online]. Available: https://www.eaton.com/content/dam/eaton/ products / electronic - components / resources / data - sheet / eaton - cl1208 - multi-phase-power-inductors-data-sheet.pdf. 46 https://doi.org/10.30420/565822053 https://www.analog.com/media/en/technical-documentation/data-sheets/lt8627sp.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/lt8627sp.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/6909fa.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/6909fa.pdf https://www.eaton.com/content/dam/eaton/products/electronic-components/resources/data-sheet/eaton-cl1208-multi-phase-power-inductors-data-sheet.pdf https://www.eaton.com/content/dam/eaton/products/electronic-components/resources/data-sheet/eaton-cl1208-multi-phase-power-inductors-data-sheet.pdf https://www.eaton.com/content/dam/eaton/products/electronic-components/resources/data-sheet/eaton-cl1208-multi-phase-power-inductors-data-sheet.pdf A Simulation models Figure A.1: PH1 of simulation model with DL. I A. Simulation models Figure A.2: PH3 of simulation model with DL. Figure A.3: Clock generator LTC6909. II A. Simulation models Figure A.4: Parameters used for simulation. Figure A.5: Section of output capacitors. III A. Simulation models Figure A.6: Six Phase CL. IV DEPARTMENT OF SOME SUBJECT OR TECHNOLOGY CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden www.chalmers.se www.chalmers.se List of Acronyms Introduction Background Aim Theory Buck converter Multi-phase buck converter (MPBC) Discrete inductors in MPBCs Output capacitors in MPBCs Coupled inductors Notch Coupled Inductor Trans-inductor Voltage Regulator Integrated Circuit Operation Pins Multiphase operation System stability Simulation software Case setup Testboard Modifications Simulation setup Investigation parameters Differences between simulations and testboard Inductors Output Capacitance Lab setup Equipment Adjustments Implementation LT8627SP General simulation model Stability analysis Efficiency Step load response Power system rejection Building & testing physical model Stability analysis Efficiency Voltage ripple Results Simulations Stability Response Step Response Efficiency Power system rejection ratio Lab Stability measurement Efficiency Voltage Ripple Conclusion Simulation models