Per-core Power Estimation and Power Aware Scheduling Strategies for CMPs

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/136455
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Type: Examensarbete för masterexamen
Master Thesis
Title: Per-core Power Estimation and Power Aware Scheduling Strategies for CMPs
Authors: Goel, Bhavishya
Abstract: The problem of accurately estimating the processor power consumption has generated significant interest among computer architects in the last decade. With the focus on green computing intensifying, increasing number of task management applications have become power aware in last few years. Hence, the need for a fast and accurate power model is greater than ever. In addition, today’s multi-core processors demand task schedulers to balance the performance requirements, power budget and thermal constraints. This thesis addresses this requirement by presenting a percore power model based upon performance monitoring counters and temperature data. PMC based power models provide a straightforward and fast way of analyzing the activity of processor’s underlying microarchitecture. The advantage of our model is that it is general enough to be ported and scaled across different platforms with ease, fast enough to be used online by task schedulers, and it requires no knowledge of individual applications. During this thesis work, we validated the model on three different (two- to eight-core) platforms. The model accurately estimates core power consumption, exhibiting 1.8%-4.8% per-suite median error on the NAS , SPEC OMP , and SPEC 2006 benchmarks (and 1.6%-4.4% overall).
Keywords: Datorteknik;Computer Engineering
Issue Date: 2011
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/136455
Collection:Examensarbeten för masterexamen // Master Theses



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