Instruction Decoder design for the FlexCore Processor
Typ
Examensarbete för masterexamen
Master Thesis
Master Thesis
Program
Publicerad
2010
Författare
BUZDAR, ABDUL REHMAN
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
The goal of this project is to design an instruction decoder for the FlexCore processor based on an instruction compression scheme that would be used in implementing the instruction decoder circuitry. The instruction decoder is implemented using VHDL and an optimal compression scheme considering the FlexCore processor requirements. Later the VHDL description of the instruction decoder was synthesized using Cadence RTL compiler to study the impact of instruction decoder on the FlexCore processor performance in terms of timing, area and power requirements. The report also gives an analysis of various parameters of the compression scheme that would have an impact on the overall performance of the instruction decoder and eventually the FlexCore.
Beskrivning
Ämne/nyckelord
Informations- och kommunikationsteknik , Grundläggande vetenskaper , Innovation och entreprenörskap (nyttiggörande) , Datorteknik , Information & Communication Technology , Basic Sciences , Innovation & Entrepreneurship , Computer Engineering