Network Implementation in an FPGA

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/256623
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Type: Examensarbete för masterexamen
Master Thesis
Title: Network Implementation in an FPGA
Authors: Furufors, Anders
Abstract: A limited network stack is implemented on an FPGA for use in nuclear physics experiments to transfer data directly from front-end electronics to a PC over Ethernet. This is done using an FPGA board equipped with a connector attached to a PHY chip. Code was written for this FPGA to handle the physical and most of the link layer. Higher layers of network communication were implemented in the FPGA, using a hardware design called Fakernet. Fakernet handles the rest of the link layer as well as network and transport layer protocols. This results in a design that sufficiently handles protocols needed for establishing a connection between nodes on a network (ICMP, ARP) and to be configured using a UDP interface. It is able to send data to a PC using TCP, reaching line speed with the PHY chip’s 100 Mb/s interface while at the same time having low resource usage, occupying less than 2 per cent of the LUTs of an FPGA used in the type of experiment the design is considered for. This design was tested for various situations and restrictions and it is concluded that it has potential for being used in real experiments in the future even though Fakernet is not yet fully developed.
Keywords: Fysik;Physical Sciences
Issue Date: 2019
Publisher: Chalmers tekniska högskola / Institutionen för fysik (Chalmers)
Chalmers University of Technology / Department of Physics (Chalmers)
URI: https://hdl.handle.net/20.500.12380/256623
Collection:Examensarbeten för masterexamen // Master Theses



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