Investigation of optimized topology for AC/DC Power supply unit in telecom in- dustry Master of Science Thesis Habtamu Masresha Teklay Haile Department of Energy and Environment CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2019 Investigation of optimized topology for AC/DC power supply unit in telecom industry A Master of Science thesis in which different AC/DC converter topologies are studied and compared Habtamu Masresha Teklay Haile Department of Energy and Environment Division of Electric Power Engineering Chalmers University of Technology Gothenburg, Sweden 2019 Investigation of optimized topology for AC/DC power supply unit in telecom indus- try. A Master of Science thesis in which different AC/DC converter topologies are stud- ied and compared in terms of efficiency, power density and cost. Habtamu Masresha & Teklay Haile © Habtamu Masresha & Teklay Haile, 2019. Supervisor: Mikael Högrud, Ericsson Examiner: Torbjörn Thiringer, Department of Energy and Environment Department of Energy and Environment Division of Electric Power Engineering Chalmers University of Technology SE-412 96 Gothenburg Telephone +46 31 772 1000 Cover: AC/DC converter made of bridgeless PFC and half bridge LLC converters Typeset in LATEX Gothenburg, Sweden 2019 iv Investigation of an optimized toplogy for AC/DC power supply unit in telecom in- dustry Habtamu Masresha Teklay Haile Department of Energy and Environment Electric Power Engineering Chalmers University of Technology Abstract Nowadays most power electronics converters are becoming more efficient and cost effective, and yet there is always a room left for improvement. This Master thesis deals with AC/DC power supply units in telecom industry which is implemented by a two-stage approach, which includes a power factor correction (PFC) stage followed by an isolated DC/DC stage. A literature study has been conducted to choose suitable topology candidates for telecom industry for power levels around 500W, 1kW and 2kW. The topology selec- tion has been done considering efficiency, power density and cost. Active boost/- classical boost, interleaved and bridgeless PFC are chosen to be suitable for further studies. Similarly, half bridge, full bridge and interleaved half bridge LLC reso- nant converters have also been selected for further study. This study indicates that, the bridgeless PFC converter, at 230V input, shows high efficiency across the given power range and has a peak efficiency of 98.5%. The half bridge LLC resonant converter is chosen to be efficient and cost effective for around 500W with a peak efficiency of 97.5%. The full bridge LLC resonant converter is chosen for power levels around 1kW with a peak efficiency of 97.5%. For a power range around 2kW, the interleaved half bridge LLC resonant converter is chosen with a peak efficiency of 97.7%. The combination of the PFC stage and LLC stage gives the AC/DC power supply unit (PSU). With the selected topology combinations, this converter can achieve a peak efficiency of 96.0%, 95.9% and 95.6% around 500W, 1kW and 2kW respectively. Keywords: PFC, LLC, PSU, LLC, Resounant converters v Acknowledgements We wish to thank our supervisor at Ericsson, Mikael Högrud, for his continues technical support. We also want to express our deepest gratitude for Xiaolong Yue and Michael Heitmann, at Ericsson, for giving us the opportunity to work this master thesis with them and also for helping us all the way through this thesis. We also want to thank our examiner, Torbjörn Thiringer, for the continues support and guidance throughout this project. vii Contents 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Problem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.5 Environmental and ethical aspects . . . . . . . . . . . . . . . . . . . . 2 2 Theory 5 2.1 Background on AC/DC converters . . . . . . . . . . . . . . . . . . . . 5 2.2 Overview on active PFC topologies . . . . . . . . . . . . . . . . . . . 6 2.3 Active PFC converters and their mode of conduction . . . . . . . . . 8 2.3.1 Active boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 Interleaved boost PFC . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 Bridgeless boost PFC . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Losses and component sizing of PFC stage . . . . . . . . . . . . . . . 14 2.4.1 Diode bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2 Boost Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.3 Switching element . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.3.1 MOSFET switching waveforms . . . . . . . . . . . . 19 2.4.4 Boost diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.5 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.5.1 Hold up time requirement in telecom . . . . . . . . . 23 2.5 Small signal model of PFC converters . . . . . . . . . . . . . . . . . . 23 2.5.1 Small signal model of active boost PFC . . . . . . . . . . . . . 24 2.5.2 Small signal model of interleaved boost PFC . . . . . . . . . . 26 2.5.3 Small signal model of bridgeless PFC . . . . . . . . . . . . . . 27 2.6 Overview on isolated DC-DC converter topologies . . . . . . . . . . . 28 2.7 LLC resonant converters . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7.1 Half-bridge LLC resonant converter . . . . . . . . . . . . . . . 32 2.7.2 Full-bridge LLC resonant converter . . . . . . . . . . . . . . . 32 2.7.3 Interleaved half bridge LLC converter . . . . . . . . . . . . . . 32 2.8 Losses and component sizing of LLC stage . . . . . . . . . . . . . . . 33 2.8.1 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.2 Resonant tank inductor and capacitor ESR losses . . . . . . . 36 2.8.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.4 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 37 ix Contents 2.8.5 Small signal model of LLC resonant converter . . . . . . . . . 37 3 Method 43 3.1 Modeling of the selected AC/DC converter topologies . . . . . . . . . 43 3.2 Modeling of the PFC stage . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.1 Diode bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.4 Boost diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.5 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.6 Simulation model of PFC . . . . . . . . . . . . . . . . . . . . 48 3.3 Modeling of LLC resonant converter . . . . . . . . . . . . . . . . . . . 48 3.3.1 Simulation model of LLC . . . . . . . . . . . . . . . . . . . . . 53 4 Results 55 4.1 Loss distribution of the PFC stage . . . . . . . . . . . . . . . . . . . 55 4.2 Loss distribution of the LLC resonant converter . . . . . . . . . . . . 59 4.3 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.1 Investment cost . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.2 Operating cost . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.3 Net present worth . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4 Power density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.5 Efficiency of the AC/DC converter . . . . . . . . . . . . . . . . . . . 63 5 Conclusion 65 5.1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Bibliography 67 A Appendix 1 I x 1 Introduction 1.1 Background Power supply units (PSU) are used almost in every application that uses electrical power as a primary source. In most of the applications, the contribution of the PSU is very important in energy savings, thus saving money. One of the major areas that involves the use of an AC/DC power supply units is telecom industry. The 5G network, the Fifth-generation wireless network, is the latest technology in telecom industry which will increase the data transfer and responsiveness of wireless networks. Advanced Antenna System (AAS) and Antenna Integrated Radio (AIR) unit are important products of 5G. To achieve higher system integration, higher power density and higher efficiency are required for the power supplies of AAS and AIR products, and such requirements bring more challenges to the design of the AC/DC PSU used in telecom industry. The AC/DC PSU in telecom industry is usually implemented by a two-stage ap- proach, which includes a power factor correction (PFC) stage followed by an isolated DC-DC stage [1]. To improve the PSU’s efficiency and power density, the switching frequency of both stages shall be pushed to higher frequency regions, then the selec- tion of the most optimized topology becomes one of the critical issues that should be investigated for an AC/DC PSU design. 1.2 Aim The aim of this thesis work is to investigate the most optimized topologies for AC/DC power supply units with different power levels, for example below 500W, around 1kW and 2kW by considering efficiency, power density and cost. 1.3 Delimitations Theoretical and simulation models shall be investigated for selected AC/DC con- verter topologies based on previous work and literature review for different power rating. Analysis will be made based on efficiency, power densities and cost and the optimized converter topology will be selected for different power levels. As a constraint the following limitations are set: 1 1. Introduction • This masters thesis does not include hardware design of the selected topologies. • The topologies are going to be simulated in open loop control since the design of closed loop control is out of scope. • For the DC/DC stage only LLC converters of different topologies will be stud- ied and other DC/DC converter topologies are excluded. 1.4 Problem description Due to high frequency operation of 5G antennas in telecom industry the operation ranges of this antennas might be limited to short distance ranges. Due to easy availability of AC grid and unavailability of DC supply voltage in the streets, an optimized topology of AC/DC converters should be investigated in terms of their efficiency, cost and power density. Based on literature studies, key topologies will be selected and further investigation. The efficiency curves and power losses shall be calculated and verified via simulation to find the most optimized topology. 1.5 Environmental and ethical aspects This thesis work deals with optimized topology of AC/DC converters which deals, mostly, with efficiency of the converters. The use of optimized converters in terms of efficiency saves energy and money in the long run. The way electricity is consumed also affects the environment. The power consumption consumed by one converter might be very low, but with the presence of millions of these converters connected to the grid will have a huge impact on the grid and consequently on the environment one way or another. In US, studies indicate that about half of the electricity generated will be processed by some kind of electronics device and in case of extreme power quality failure, the cumulative effect can lead to power outage as in 2003 in New York[2]. To decrease the effect of low power quality, standard like IEEE 519 and IEC 1000-3-2 should be considered and the converters should meet the EMC certifications. Another perspective is to understand and to minimize the environmental impact based on how the raw materials are extracted for the specific topology design and different choices or designs should be considered which affects the environment less. Many developed countries have a long term commitment fighting global warming and reduce carbon impact. For example, in Britain in 2014, BT Group plc (trading as BT and formerly British Telecom) developed a rectifier replacement program in the UK network, a trial of Huawei’s super high efficiency rectifier within a BT operational site is to be implemented. The efficiency of the new front end rectifiers were 98% which replaces the old ones with efficiency 96%[3]. The study indicates that, in 5 years investment view, the rectifiers with efficiency of 96% has a return on investment of 55 weeks whereas the rectifiers with 98% efficiency has a return on 2 1. Introduction investment of 52 weeks. Furthermore, the study indicates that cumulative savings over 5 year’s use of 98% efficiency rectifiers achieves £9M more savings than using 96% efficiency rectifiers. This shows efficient power converters have a great impact on environment and have a huge operational benefit. 3 1. Introduction 4 2 Theory 2.1 Background on AC/DC converters Alternating current (AC) supply is a very efficient way of transferring electrical power and since most of electronic devices work in direct current (DC) power sup- ply, the AC source should be converted to DC. The easiest way of converting AC to DC is to use four diodes as in bridge rectifier and connecting a capacitor as filter as shown in Figure 2.2. But this kind of rectifiers does not meet harmonics standards like IEC6000-3-2[4] and have low efficiency. Furthermore, there is no way of con- trolling the current in the rectifier. These drawbacks and limitations give rise the development of high efficiency AC/DC converters. Nowadays, two stage approach of AC/DC converters are implemented in telecom industry with a basic layout as shown in Figure 2.1. The EMI filter, usually made of passive components, reduces high frequency noises and helps only the fundamental component of the AC current passes through the converter. The PFC block shapes the input current in such a way that it has the same waveform as the rectified AC voltage and help the converter have a power factor close to 1. The DC/DC converter changes the DC output of the PFC converter and changes to a regulated and required voltage level. This stage can be implemented with switch mode power supply or with resonance converters. Resonant converters provide high efficiency operations since the switch in the converter works in zero voltage and zero current switching, which reduces the switching loss of the switch. To have a high power density and efficiency of the DC/DC stage different resonant converter topologies are available as it will be explained more in the coming sections. The effi- ciency and performance of the AC/DC converter is then determined by the combined efficiency and performance of the PFC and LLC stages. Figure 2.1: General layout of AC/DC converters 5 2. Theory 2.2 Overview on active PFC topologies As it has been introduced in the previous section, the AC/DC power conversion usually implemented in two power stages. The first stage consists of a power factor correction stage and the second stage being a DC/DC converter. The classical AC/DC conversion circuit uses four diodes as in a bridge rectifier configuration to rectify the sinusoidal AC voltage and a capacitor connected to the output to filter out the voltage ripple as shown in Figure 2.2. Figure 2.2: Bridge rectifier circuit The current from the supply flows to the output only when the capacitor voltage is less than the input voltage. Consequently, the current consumed is not sinusoidal and is rather distorted as shown in Figure 2.3. The power factor of this type of converter is usually around 0.7 [5], which greatly affects the power quality and does not meet industry standards. Figure 2.3: Voltage and input current of bridge rectifier circuit In order to reduce the total harmonic distortion (THD) of the input current and to improve its power factor, power factor corrector (PFC) circuits are implemented. 6 2. Theory Passive versus active PFCs broadly classified as passive and active PFC controllers. Passive PFC con- trollers use passive devices like inductors to shape the current waveform and do not use any control mechanism whereas active PFC controllers use different control mechanisms to shape the current input. Usually passive PFCs are not implemented if the power level is higher than 400W because of their bulky size, high cost and poor performance [6]. Active PFC converters provide a much better power factor of the current and they can be implemented in so many different typologies. Many of the topology imple- mentations depend on the type application such as input/output voltage require- ments. One way of classifying PFC converters is by the use of diode rectifier bridge as a means of changing the AC/ voltage to DC voltage waveform and control the input current. The most commonly used PFC topology of these kind is the active boost PFC converter, whereas PFCs based on flyback converter, SEPIC converter and CUK converter can also be implemented as PFC depending on the applica- tion[7]. The use of diode bridge rectifier increases the conduction losses in the PFC and creates a thermal stress in the bridge and usually requires a heat sink. Bridgeless The used of bridge circuit brings issues with power loss and thermal management. PFC converters that does not need bridge rectifier are known as bridgeless PFC converters. These converter typologies have higher efficiency as compared with the previous group of PFC topologies. Basic bridgeless PFC, Semi bridgeless PFC and back to back bridgeless PFC can lie into this category[8]. As stated in [8], most of these type of topologies experience a higher level of electro-magnetic interference (EMI) issues because of their topology. Different modifications and types of bridge- less topologies are implemented to decrease this EMI issues and semi-bridgeless PFC is one of those. Interleaved Another group of PFC can be classified as interleaved PFCs. Interleaving means channeling the power flow from the input to the output into two or more separate paths and add them at the output point. By doing this, the current ripple on both at the input and at the output of the converter is reduced. As the number of in- terleaved branches increase the power rating also increases. Another advantage of this approach is better thermal performance as it uses two inductors which are half the size of the basic active boost PFC as will be explained later. The use of two inductors can increase the thermal performance of the converter as well. Wide band-gap switches: SiC and GaN The bottleneck with increasing the switching frequency to decrease the size of pas- sive devices is that it increases the switching losses of the MOSFETs significantly. The development of new types of switches such as gallium nitride (GaN) and Silicon carbide (SiC) switches, lead the PFC converter to different types of topology known as the totem pole PFC. In wide gap switch, because of the absence reverse recovery charges (Qrr), the switching losses significantly reduces and the switching frequency 7 2. Theory can be pushed to a higher level resulting small converter size and increased power density[9]. Table 2.1 shows some of the PFC topologies that have high efficiency. The table does not include all the PFC topologies but summarizes the most common PFC topology implementations with their reference document. Table 2.1: High Efficiency PFC converters No Topology Feature Power (W) Peak Efficiency (%) Ref. 1 Buck High gain 500 98.5 [10] Cascaded 2000 97 [11] 2 SEPIC Uses SiC MOSFETs 1000 95.3 [12] 3 Cuk Synchronous rectifier 150 95 [13] 4 Active boost Soft switching 500 97 [14] Interleaved 700 98.4 [15] 5 Bridgeless active boost Phase shifted 1000 98.6 [16] Three level; Interleaved 3000 98.6 [17] Dual-boost 3200 99.33 [18] 6 Totem pole Uses MOSFETs 1600 98.05 [19] Uses SiC MOSFETs 2000 98.5 [20] Uses GaN 3000 99.1 [9] 2.3 Active PFC converters and their mode of con- duction As it has been mentioned earlier, the main goal of this PFC converter is to charge and discharge the inductor by controlling the switch to control the average current flowing through the inductor, i.e. input current, have the same shape as the rectified voltage waveform. The mode of conduction in PFC converters refers to state or value of the current in the boost inductor. In continues conduction mode (CCM) the current in the inductor will not reach zero in one switching period. which implies that the difference between the RMS and peak currents through the inductor are minimum which makes this mode of conduction popular at higher power levels. Furthermore, the EMI filter design is simplified since the input current through the PFC is always continues. In this conduction mode, hard switching takes place which apparently increase the losses in switch and diode as will be explained in the following sections. Figure 2.4 show the waveforms in CCM where Vrect is the rectified voltage, IL is instantaneous inductor current and Iavg is the average current of inductor. 8 2. Theory Figure 2.4: PFC waveforms in continues conduction mode The second conduction mode, critical or boundary conduction mode (BCM), is a type of conduction in which the next switching cycle starts when the inductor current reaches zero as shown in Figure 2.5. One advantage of this conduction mode is that the reverse recovery loss of the boost diode is almost negligible and the turn on losses in the switch will be zero since the current reaches zero prior to turning on the MOSFET. Although this conduction mode provides soft switching while turning on the MOSFET, it exposes the switch, the diode and the inductor to high current stress. Another disadvantage of this mode of conduction comes when designing EMI filter. For example to keep the same size of EMI filter in DCM mode, which operates in CCM with a switching frequency in kHz range, is to push the switching frequency in range of MHz, apparently, this results in large switching losses[21]. Figure 2.5: PFC waveforms in boundary conduction mode Discontinues conduction mode (DCM) is when the current through the inductor is discontinues. While implementing DCM, using one control loop is enough to assure good power factor while maintaining constant output power. Because of the reason that the MOSFET, the inductor and the boost diode stress and problems with conducted emission, the use of converters operating in DCM is limited to low power range, i.e < 250W[22]. The waveforms in DCM are shown in Figure 2.6. 9 2. Theory Figure 2.6: PFC waveforms in discontinues conduction mode 2.3.1 Active boost PFC Active boost PFC converter uses a diode bridge to rectify the AC voltage to pulsating DC and then use an active boost DC to DC converter to control the input current i.e. controlling the power factor. The active boost PFC topology is the most used topology because of its simple power circuit and easy control of the input inductor current so that the current will have the same waveform of the rectified ac voltage [23]. This topology is also a basic topology as most of other PFC converters are derived from this topology. Active boost PFC converter is an ideal PFC controller especially if the voltage at the output is required to be higher than the input and if another DC/DC stage is connected to the PFC output. This is because the PFC stage will act as a pre- voltage regulator for the DC/DC stage. There are different ways of controlling the input current in the boost configuration by controlling the switch shown in Figure 2.7. Average current control mode, hysteresis current control mode and peak current control mode are ways of controlling the current in the inductor but average current control mode is commonly used one because of the simplicity[6]. Figure 2.7: Boost PFC circuit The main operation of an active boost PFC is the same as a DC/DC boost converter. The difference is that the input for the PFC is a pulsating DC voltage. In some PFC designs, an input capacitor is connected after the bridge rectifier to decrease the current ripple in the boost inductor. This will help in reducing the physical size 10 2. Theory of the inductor. Figure 2.8 shows the current paths when the switch, Sw, closes and opens. In Figure 2.8a, the current from Vin will charge up the inductor and the charge stored in the capacitor makes the current flow to the load. In Figure 2.8b the current stored in the inductor starts to flow to the output capacitor and charges it. (a) Turn on (b) turn off Figure 2.8: The current paths when the switch turns on and turns off From the fact that the average inductor voltage over one time period is zero, if CCM is considered, applying KVL in Figure 2.8a when the switch is on, and Figure 2.8b when the switch is off, we get Vrectton + (Vrect − Vo)toff = 0 (2.1) where ton is the on time period for the switch and toff is the off time period for the switch. Rearranging (2.1), the ratio between Vin and Vo can be found as follows Vo |Vrect| = 1 1− d (2.2) where d is the duty cycle and and Vrect is the rectified voltage. Based on the equations derived above, the average model of the active boost PFC can be drawn as shown in Figure 2.9. Figure 2.9: Average model of active boost PFC in CCM In CCM, the boost diode, D5, in Figure 2.7, turns off by interrupting the current flowing through it which causes reverse recovery losses in the diode. This phenomena also imposes higher turn on losses in the switch, Sw. Furthermore, this topology requires good EMI filter since the current ripple in the inductor is the same as the input current ripple. This topology is usually used for power range of less than 1kW. 11 2. Theory 2.3.2 Interleaved boost PFC Interleaving approach is used to channel the current flowing path into two or more phases so that the output current is the sum of each individual phases. Figure 2.10 shows single phase two leg interleaved PFC topology. The two switches, Sw1 and Sw2, operates 180◦ out of phase. The input current will flow in both inductors, L1 and L2, and the total current will be the sum of the currents passing through the two inductors. Figure 2.10: Interleaved PFC converter The operational principles of an interleaved boost PFC is exactly the same as the active boost PFC and for one leg, for example for inductor, L1, and switch Sw1, Figure 2.8 can be used to see the current flowing paths. Since this topology uses two inductors, L1 and L2, each with half size of the boost PFC, the thermal performance of the converter will improve. The efficiency of this converter is also higher as compared with the active boost PFC since the power is channeled through two paths which decreases the conduction losses of the inductor, the boost diode and the MOSFET by half. Furthermore, the stress across the switches reduces. Interleaved operation is usually preferred over the active boost PFC if the power level is higher than 1kW. The inductor current ripple in active boost PFC is the same as the input current ripple while in the interleaving approach, the ratio of the supply ripple current to inductor’s ripple current can vary depending on the duty cycle. Current ripple cancellation both in the input and output side of interleaved PFC is considered as the major advantage over the active boost PFC. The ripple in the input current, ∆iin, can be written as (2.3) for duty cycle greater than 0.5 and less than 0.5[24]. ∆iin =  ∆iL 1−2D 1−D , forD ≤ 0.5 ∆iL 2D−1 D , forD ≥ 0.5 (2.3) Figure 2.11 show how the ripple current cancels in the two legs as a function of duty cycle. Consequently, the size of the EMI filter reduces as a result of ripple current cancellation. 12 2. Theory Figure 2.11: Inductor ripple current cancellation 2.3.3 Bridgeless boost PFC In the bridgeless PFC, the diode bridge used to rectify the AC input voltage is not needed. The bridgeless PFC discussed in [16], which is the same as the one shown in Figure 2.12 without diode D3 and D4, has a major disadvantage of high EMI due to a switch voltage changing from negative to positive values which is usually not recommended for telecom applications. The solution is to use two diodes D3 and D4 as a current return path and connects the input neutral to the output neutral as shown in Figure 2.12. Due to these diodes, and because of the presence of two boost inductors this topology is also known as the semi-bridgeless PFC or dual-boost semi-bridgeless PFC. Consequently, this topology can achieve higher efficiency as it reduces the number of components in the current flowing path. In addition to high efficiency, this topology also has high power density and better heat spot distribution and this provides less cooling effort[25]. Figure 2.12: Bridgeless PFC The operation principles of the bridgeless PFC for the positive AC cycle and negative AC cycle are symmetrical, thus only the positive half cycle is discussed here. The classification for positive and negative AC cycles comes from the absence of the bridge rectifier. 13 2. Theory Figure 2.13: For positive AC cycle and SW1 is on and SW2 is off When the switch, Sw1, is conducting, the inductor, L1, will charge up and the return current flows back to the source through D3. The return current also uses the body diode of the second switch, Sw2, although it can be ignored when explaining the working principle of this PFC. Since the flow of the reverse current through these two separate channels, through one diode and body diode of one of the MOSFETs, will reduce the losses in the diode and increase the MOSFET losses. The current flows through the body diode just because of the circuit configuration. Meanwhile, the voltage stored in the output capacitor flows to the load. During this interval the voltage across inductor L1 can be expressed as VL1 = L diL1 dt = Vs (2.4) Figure 2.14: For positive AC cycle and both switches are off When the switch, Sw1, is open then the energy stored in the inductor flows to the load as shown in Figure 2.14. Which basically results in the same operating phenomenon as the active boost PFC. For the negative AC cycle the same operation continues for the second inductor, L2. 2.4 Losses and component sizing of PFC stage The sizing of components in the PFC depends on different parameters like maximum power output, maximum voltage and current capabilities of the converter. The efficiency of the AC/DC converters directly related to the losses in the components that build up the converter. All the three topologies contain diode bridge rectifier (also known as slow diodes in bridgless PFC), inductor, MOSFETs, boost diode 14 2. Theory and output capacitor. The sizing of each device and the losses associated with each component will be in this section. 2.4.1 Diode bridge The diode bridge in active boost and interleaved PFC stages are used to rectify the AC voltage in to a pulsating DC waveform so that it is easier to shape the current through an inductor have the same waveform as the rectified DC. The maximum break down voltage or reverse voltage of the diode rectifier should be at least equal to the output voltage of the boost PFC circuit. If, for example, the output voltage of the PFC is 400V, then the reveres voltage capability should be 450V or 500V so that the bridge rectifier can perform better with less voltage stress. Another criterion choosing the bridge rectifier is that it should have a low voltage drop and low forward resistance as much as possible so that the losses would be minimized. Diode losses can be classified into conduction losses, which comes from the resistive part of the diode while its conducting, and turn off loss which is caused by the reverse recovery of the diode. Figure 2.15 show a representation of a power loss in a diode due to its forward resistance, Rf and due to its forward voltage drop Vf . Figure 2.15: Representation of a diode The turn off losses of diode or reverse recovery losses are caused by the release of charges when the diode goes from conducting state to blocking state. For grid connected bridge rectifiers, where the mains frequency is 50 or 60 Hz, the reverse recovery losses are usually ignored as the switching takes place naturally and the current through the diode is zero while switching, and during forward biased the typical voltage drop, Vf , is 0.8V. The power loss of the diode can be given by (3.2.1) as a function of temperature where Iav and Irms are the average input current and RMS value of the current passing through the diode when it is forward biased. Pdiode,c = Vf (T )Iav +Rf (T )I2 rms (2.5) The diode parameters, Vf and Rf , can be found from the diode specification or datasheet. For bridgeless PFC, the losses due to the slow diodes can also be calculated using (2.5) but the average current passing through the diode changes as nearly half of the current will return back through the body diodes of the MOSFET. This further will be explained in the next chapter. 15 2. Theory 2.4.2 Boost Inductor The inductor in any PFC topology is the most important circuit component because of the reason that the current in the inductor will neither go to zero nor will reach rated value instantaneously, so its evident that it is possible to shape the current passing through it. The size of the inductor, apart from the RMS current through it, can be determined from the ripple current that is allowed to pass through it. Usually the ripple current can be given as the percentage of the maximum input current. For all the three topologies discussed above, the inductor size can be determined as follows. From (2.1), when switch Sw is off, the inductor voltage can be, respectively expressed as VL = (Vrect − Vo)toff (2.6) Equation (2.6) holds true for both active boost and interleaved PFC topologies. For bridgeless topology, the rectified voltage,Vrect, should be replaced with the supply voltage, Vs. (2.6) can also be expressed as VL = L diL dt = (Vrect − Vo)toff (2.7) During turn off, the inductor voltage is decreasing which mean VL will have a negative value. Replacing the off period by (1-d)/fs, where fs is switching frequency and rearranging (2.7) gives L = (Vo − Vrect) (1− d) ∆iLfs (2.8) Equation (2.8) can be used to determine the size of the inductor. Furthermore, in [26], the maximum ripple current is experienced in the inductor when the input voltage is at its peak. Then, for active boost and interleaved PFC topologies, (2.8) can be written as L = (Vo − √ 2Vrect) (1− d) ∆iLfs (2.9) where ∆iL is the ripple current in the inductor and it can be given by the following equation where η is the efficiency of the PFC, % ripple is the ripple current in the inductor in percentage ∆iL = Po ηVrect,min %ripple (2.10) by combining (2.9) and (2.10), for active boost and interleaved PFC, the minimum inductor size can be given as L = 1 %ripple 1 η V 2 rect,min Po fs (1− √ 2Vrect,min Vo ) (2.11) and for bridgeless PFC, the minimum inductor size can be expressed as L = 1 %ripple 1 η V 2 s,min Po fs (1− √ 2Vs,min Vo ) (2.12) In practice, the size of the inductance value for the PFC stage is slightly higher than the one calculated using (2.12). 16 2. Theory Inductor core selection Power inductors require a core and air gap within the core structure to increase the energy stored in the inductor and preventing the core from saturation. The core should be chosen in such a way that it should have less volume and less core loss. The air gap in the core can be distributed all over the core as in powdered cores or it can be discrete as in ferrite cores. In powdered core the air gap is distributed in the core since the core is made of different materials powdered together as an alloy. One advantage of powdered core is that it decreases fringing loss. This loss is due to the scattering of magnetic flux lines out of the core path and is emitted into the air. Ferrite cores uses discrete air gap in the core structure which leads to low AC core loss at high frequency but are expensive as compared with powdered cores[27]. Inductor wire selection The inductor wire will form a turn around the core and is selected based on the maximum current. It should meet the requirements that one it should be thick so that the resistance is small and two its should be possible to form the required number of turns around the core. Inductor losses Inductor losses can be divided into core losses and copper losses. The core loss in an inductor can be found from the following Steinmetz’s equation(2.13), which is an empirical formula used to calculate the core loss per unit volume. Pcore = k fas B b max (2.13) where fs is switching frequency, Bmax is the maximum flux density. k, a and b are constants which depends on the type of core. Another way of calculating or estimating the core loss at specific switching frequency is to use core suppliers’ curve fit equations. This way of calculating core loss is explain in the next chapter. Copper losses are basically the resistive losses present in the copper winding of the inductor. Once the type of inductor wire is selected, then the resistance of the copper wire can be calculated by RDC = ρl A (2.14) where ρ is the resistivity of the copper wire, L is the length of to form the required turns in the inductor and A is the cross sectional area of the copper wire selected. Then the copper loss can be easly calculated using (2.15), where iL,rms is the RMS current through the inductor Pcopper = i2L,rmsRDC (2.15) 17 2. Theory 2.4.3 Switching element The selection of switching element in a PFC depends on different parameters. The first requirement is the switching frequency of the system. Usually IGBT switches are used in high voltage low switching frequency applications while MOSFETs are usually used in high switching frequency low voltage applications. The switching frequency of the PFC itself should optimize the size of passive components and switching losses. Usually the switching frequency in a PFC is chosen to be between 25kHz and 150kHz. As mentioned in[28] most of DC to DC and AC to DC convert- ers usually fail to meet the requirements of electromagnetic compatibility (EMC) certification in their first design loop. If size is an issue the switching frequency should be pushed higher to decrease the size of passive components and a proper size of EMI filter should be designed. The most important parameters selecting a MOSFET are drain to source voltage rating, rated drain to source current rating VDS, the on state resistance, RDS,on and the gate charge, Qg. Furthermore, in order to have as low switching losses as possible, the turn on and turn off transient times should have be low. MOSFET losses Ideally, MOSFETs are represented as an ideal switch i.e. zero resistance while it’s in on state and infinite resistance when it’s in off state. In real scenarios this is a wrong assumption and a proper MOSFET model should be investigated to determine the losses associated with the it. MOSFETs have four types of losses. These are switching losses, conduction losses, gate losses, and MOSFET’s output capacitance or MOSFET’s body diode losses. These losses can be determined using three methods[29]. The first method can be equating the turn on and turn off time transients to estimate the losses. The second method is to use the datasheet information to approximate MOSFET losses. The last method is to physically model MOSFET’s parameters such as doping density, geometry, and to use finite element analysis software like COMSOL to evaluate the losses. Conduction losses in MOSFETs are caused by the continues voltage drop in the MOSFET while it is conducting because of the presence of the on time resistance of a MOSFET, RDS,on and is given by (2.17). For active boost and bridgeless PFC the drain to source current of a MOSFET can be given by IDS,rms = Pout ηVrect √ 2− 16Vrect 3πVo (2.16) For interleaved PFC the drain to source current is half of the one given in (2.16). Although it takes a few nano seconds for the MOSFET to turn on and to turn off, switching losses of a MOSFET are significant, because of their high switching frequency applications. These MOSFET switching losses are caused by the voltage and current overlap area while the MOSFET turns on and turns off as it will be clearly explained below. This way of switching MOSFETs is called hard switching. 18 2. Theory There are ways of implementing the PFC switch to operate in zero voltage and zero current switching by using additional circuit components[14]. This type of switch operation is called soft switching and help reduce the switching losses. As a result, the switching frequency can be pushed to a few MHz range to increase the efficiency and power density. Pconduction = i2DS,rmsRDS,on (2.17) 2.4.3.1 MOSFET switching waveforms MOSFET turn on Turn on MOSFET waveforms are shown in Figure 2.16. Before the time period t1, i.e. t0, the MOSFET was turned off and the current passing through it IDS, was zero. During the delay time, t1, the gate to source voltage,VGS increase from 0 to the threshold voltage Vth. Once this voltage level is reached, then the current start to flow from gate to source. The time period t2 is called current rise period. Since VGS is above Vth value and the current keeps flowing and reaches its final value by the end of this period, and the voltage increase from Vth to plateau voltage Vpl. During voltage fall period, t3, the gate to source voltage, VGS, is constant since the MOSFET inters into saturation region. The time period, t4 is called gate voltage rise time. In this interval the gate voltage increases to its final value to decrease the on time resistance of the MOSFET. Figure 2.16: Turn on switching transients of MOSFET It is evident that from Figure 2.16, the turn on losses occur during current rise time, t2 and voltage fall time, t3. ton = tir + tvf tir = CissRgln(Vg − Vth Vg − Vpl ) (2.18) tvf = CrssRg Vds − Vpl Vg − Vpl (2.19) 19 2. Theory now the turn on losses can be expressed as Pon = 1 2iinVotonfs (2.20) where iin is the input current, Vo is the output voltage and fs is the switching frequency. MOSFET turn-off Figure 2.17 shows the turn off transients of a MOSFET. During turn off the reverse sequence of the turn on process repeats. During the turn-off delay time interval, t5, the gate voltage, VGS, is decreasing to Vpl and the resistance of the channel increases. Whem VGS reaches its Vpl value, textitVDS starts to increase. The time period t6 is called voltage rise time. The time period t7 is the current fall period. The current IDS decreases to zero and the current will be transferred to the free-wheeling diode. The time period t8 is called Gate voltage fall time. The turn off process is completed at the end of t7 but the voltage VGS decrease to zero as the charge stored in Ciss discharges slowly. Figure 2.17: Turn off switching transients of MOSFET From Figure 2.17, the turn off losses only occur during voltage rise time, t6 and current fall time t7 which can be expressed as toff = tvr + tif tvr = CissRgln(Vpl Vth ) (2.21) tif = CrssRg Vds − Vpl Vpl (2.22) then the turn off loss can be given by Poff = 1 2iinVotofffs (2.23) 20 2. Theory The gate loss, which is the power loss dissipated while energizing the gate charges present in the MOSFET can be given by Pgate = QgVgfs (2.24) where Qg is the gate charge and Vg is the gate voltage. The loss dissipated by the output capacitance of the MOSFET can be, respectively, given by Pcoss = eossfs (2.25) where eoss is the energy stored in the output capacitor of the MOSFET. 2.4.4 Boost diode The selection or sizing of the boost diode in PFC depends on the ability to block the reverse voltage from the output and on the average current requirement. Further- more, the reverse recovery charge of the boost diode Qrr, and the on time resistance and the voltage drop across the diode while conducting should considered. Boost diode losses The losses associated with the boost diode can be divided into conduction and switching losses. During turn on, a diode can be considered as ideal switch as it turns on very fast[5], but when it switches off, it has to release the charges, stored while it was conducting, for some time period called reverse recovery time, trr. Figure 2.18 shows the reverse recovery current of boost diode in PFC converter. Figure 2.18: Diode reverse recovery current,Irr The amount of charge stored during conduction period, also known as capacitive charge, depends on the type of the diode selection. The reverse recovery loss is then calculated from Qrr found on the datasheet of the diode and this reverse recovery loss directly depends on the switching frequency. The switching losses of the boost diode can be calculated from (2.26) Pdrc = 1 2VoQrrfsw (2.26) 21 2. Theory where Vo is the voltage it has to block, in this case, it is the output voltage, and fsw is the switching frequency of the PFC. Conduction losses of the boost diode can be calculated using the same equation used to calculate the conduction losses of the diode bridge, as given in (2.5). 2.4.5 Output capacitor The output capacitor is the energy storage device and helps to smooth out the ripple voltage present at the output. It should be properly dimensioned considering hold up time requirement or allowable voltage ripple consideration. If both requirements should be considered, then the larger size should be chosen. The equation to calculate the size of the capacitor is derived from the power equation and by the amount of energy that is needed during the hold up time. Equation (2.27) is based on hold up time requirement and (2.28) is based on allowable output voltage ripple. Co = 2 Po Tholdup Vo 2 − V 2 oholdup (2.27) Co = Po 2πfg∆V Vo (2.28) In practice, the actual capacitance value used is a little bit higher than the one calculated in (2.27) and (2.28). This is to make sure that the voltage ripples as minimum as possible and the converter has to provide energy for at least for the hold up time. Capacitors are usually categorized based on the type of dielectric used. Ceramic capacitors have ceramic dielectric and aluminum electrolytic capacitors has a thin film of aluminum oxide film that cover the capacitor plates. Usually aluminum electrolytic capacitors are used where high power density is required, because of their small volume. These types of capacitors are also preferred in PFC applications since they provide high capacitance value with low equivalent series resistance (ESR). Capacitor losses The ESR of a capacitor represents the equivalent resistance present in the capacitor. ESR of a capacitor can be determined from three methods. The first method is to measure it on the physical capacitor using ESR meter, the second way is to use dissipation factor, which is the ratio of the ESR and capacitive reactance which is roughly between 10% to 20%, at specific frequency, f, using (2.29) ESR = DF 2πfCo (2.29) where DF is the dissipation factor, Co is the capacitor value and f is a test frequency which typically 120Hz for aluminum electrolytic capacitors[30]. The third method is to use the ESR value of a capacitor from the datasheet. Once the ESR is determined, the power loss can be calculated using Pcap = icrms 2ESR (2.30) where ic,rms is the RMS current through the capacitor. 22 2. Theory 2.4.5.1 Hold up time requirement in telecom Hold up time comes from the reason that even if the input voltage level is zero because of a power outage or any other reason the circuit should provide the load for a specific amount of time called hold up time. For PFC circuits in telecom industry the hold-up time requirement is usually 20ms and for LLC it is usually 16ms. The hold up time for LLC is smaller than the PFC this is because of the reason that the PFC provides as an input for LLC, so the hold up time of the PFC should be higher or at least equal to the hold up time of the LLC so that the LLC can provide the proper amount of energy during the hold up time. 2.5 Small signal model of PFC converters In order to evaluate the losses in the PFC, an open loop control system is established to control the current input. For CCM and average current control mode, the open loop transfer function can be expressed as TFOL(s) = Gv(s) Gcc(s)Gi(s) 1 +Gcc(s)Gi(s) (2.31) where Gi(s) is inductor current to duty transfer function, Gv(s) is voltage to current transfer function and Gcc is the current compensator or current controller. In addition to the input current, if the output voltage level is required to be con- trolled, voltage controller should be implemented with feedback system as shown in Figure 2.19. In this case the closed loop controller will have internal current control loop, which should be very fast, and an outer loop voltage controller which should be very slow. TFCL(s) = Gvc(s)TFOL(s) 1 +Gvc(s)TFOL(s)LP (s) (2.32) where LP(s) is the transfer function of the low pass filter which is required to filter out high frequency components since the output voltage might contain high frequency components from the switching action. TFOL is the open loop transfer function given in (2.31). Figure 2.19: block diagram of control block for PFC in CCM 23 2. Theory The inductor current to duty transfer function, Gi(s) and the output voltage to current transfer function, Gv(s), can be found by deriving state space equation for respective PFC topologies as explain in the next subsection. Once the transfer functions are derived, for loss analysis purpose, the compensator can be designed using MATLAB’s single input single output controller design tool. The bode plot of open loop and closed loop transfer functions for each PFC converter is plotted and can be found in the appendix at the end of this document. 2.5.1 Small signal model of active boost PFC Because of the non-linearity of active boost converter, the open loop transfer function of active boost PFC can be determined by state space averaged technique. As shown in Figure 2.8, the boost PFC converter has two operating modes, one is when the switch is on and the other when the switch is off. In time domain, when the switch is on, the inductor voltage and capacitor current of active boost PFC can be written in the following two equations diL(t) dt = vrect L (2.33) dvo(t) dt = −vo(t) CRL (2.34) and when the switch is off diL(t) dt = vrect L − vo(t) L (2.35) dvo(t) dt = iL(t) C − vo(t) CRL (2.36) The above four equations can be combined together to form large signal model of the active boost PFC using state space averaged technique as explained in [31][32]. diL(t) dt = vrect L − (1− d)vo(t) L (2.37) dvo(t) dt = (1− d)iL(t) C − vo(t) CRL (2.38) The above two equation can be linearized by assuming that the variables (iL, vrect, vo, and d) by a steady state values a very small signal perturbation. This small signal model can then be used to describe the operation of converter around the steady state operation point. By replacing iL, vrect, vo, and d by steady state variable and small signal perturbation where iL=IL+îL, vrect= Vrect+ ˆvrect, vo=Vo+v̂o, and d=D+d̂. d(IL + îL) dt = (Vrect + ˆvrect) L − (1−D − d̂)Vo + v̂o L (2.39) d(Vo + v̂o) dt = (1−D − d̂)IL + îL C − Vo + v̂o CRL (2.40) 24 2. Theory Neglecting the stead state values and from the fact that the product of two small number gives even a very small number and hence ignoring those the above equation reduces to îL dt = ˆvrect L − (1−D) v̂o L + Vo d̂ L (2.41) dv̂o dt = (1−D) îL C − ILd̂− v̂o CRL (2.42) rearranging the above two equations gives[ ˙̂iL ˙̂vo ] = [ 0 −1−D L 1−D C − 1 CRL ] [ îL v̂o ] + [ 1 L Vo L 0 − IL C ] [ v̂rect d̂ ] (2.43) Equation 2.43 represents small signal AC model of active boost PFC and Figure 2.20 shows the small signal model of the PFC using dependent voltage and current sources. The small signal model diagram is drawn using [33] as a reference for one phase only. The voltage across the output, i.e. across RL in the figure below, represents the output voltage which is assumed to be constant for the small signal representation. Figure 2.20: Small signal model of boost PFC From (2.43), it is possible to derive an output to input transfer function using state space equations. Once the transfer functions are determined, then it is possible to design a compensate or a controller according to the required cut over frequency and phase margin. The cut over frequency determines the range of frequencies up to which the controllable is working or responsive and frequencies above the cut over frequencies are attenuated. The phase margin of the transfer function determines if the system is stable or not. It also shows how quickly the system responds to transient events. Gi(s) = îL d̂ = sCVo + Vo R + (1−D)IL s2LC + s L RL + (1−D)2 (2.44) in canonical form Gi(s) = îL d̂ = 2Vo RL(1−D)2 1 + sCRL 2 1 + sL RL(1−D)2 + s2LC (1−D)2 (2.45) The voltage controller transfer function can be given as the output voltage to in- ductor current transfer function Gv(s) = v̂o îL = Vo(1−D) + sLIL sCVo + 2(1−D)IL (2.46) 25 2. Theory 2.5.2 Small signal model of interleaved boost PFC The small signal modelling of the interleaved PFC can be derived the same way as explain for the small signal modeling of active boost PFC using state space averaging technique. Unlike active boost PFC, interleaved PFC does not only have two operating modes, instead it has four and if the average duty cycle is less than 0.5, both switches will not be turned on at the same time which results in three operating modes. This is because of the reason that interleaved PFC contains two separate boost PFC converters operating 180 degrees out of phase. These two separate legs are assumed to operate identically to derive the transfer function of the model. The first operating states is when Sw1 is on and Sw2 is off in Figure 2.10. The equations governing this state are given by the following set of equations. diL1(t) dt = vrect L1 (2.47a) diL2(t) dt = vrect L2 − vc L2 (2.47b) dvo(t) dt = −iL2 C − vo(t) CRL (2.47c) The second operating mode is when Sw1 is off and Sw2 is on, and the equation governing these states are diL1(t) dt = vrect L1 − vc L1 (2.48a) diL2(t) dt = vrect L2 (2.48b) dvo(t) dt = iL1 C + iL1 C − vo(t) CRL (2.48c) The third operating mode is when both Sw1 and Sw2 are off, and the equation governing these states are diL1(t) dt = vrect L1 − vo L1 (2.49a) diL2(t) dt = vrect L2 − vo L2 (2.49b) dvo(t) dt = iL1 C + iL2 C − vo(t) CRL (2.49c) Equations from (2.47a) to (2.49c) can be combined together into one average state space equation using state space averaged method[34][32], in the same way as used to derive for active boost PFC previously, to give diL1(t) dt diL2(t) dt dvo dt  =  0 0 −1−d L 0 0 −1−d L 1−d C 1−d C − 1 CRL  iL1 iL2 vo +  1 L 0 1 L 0 0 0  [vrect d ] (2.50) 26 2. Theory Equation 2.50 represents the large signal model of interleaved PFC. The small sig- nal model can be derived from the large signal model by introducing a small signal perturbation to the state values, i.e. replacing iL, vrect, vo, and d by steady state vari- able and small signal perturbation where iL=IL+îL, vrect= Vrect+ ˆvrect, vo=Vo+v̂o, and d=D+d̂. Then the small signal model can be obtained by neglecting stead state values to get  ˙̂iL1 ˙̂iL2 ˙̂vo  =  0 0 −1−D L 0 0 −1−D L 1−D C 1−D C − 1 CRL   ˆiL1 ˆiL2 v̂o +  1 L Vo L 1 L Vo L 0 iL1+iL2 C  [v̂rect d̂ ] (2.51) The two leg inductor currents are assumed to be identical so, the current to control (duty cycle) can be written as Gi(s) = ˆiL1 d̂ = ˆiL2 d̂ = sRLCVo + 2Vo s2LCRL + sL+ 2(1−D)2RL (2.52) and the output voltage to inductor current transfer function can be derived in same way to get Gv(s) = v̂o îL = vrect s2VoC (2.53) 2.5.3 Small signal model of bridgeless PFC A bridgeless boost PFC has four operation modes as interleaved PFC. For the pos- itive half cycle of supply voltage Vs, the switch Sw1 changes its state while switch Sw2, in figure 2.12, stays off and vice versa for the negative half cycle of Vs. As- suming identical inductors (L1 and L2), boost diodes (D1 and D2), slow diodes (D3 and D4) and switches (Sw1 and (Sw2), the following equations can be derived for the four operating modes. If one of the switches is open and the other is off, the equation governing the states are the same regardless of the positive or negative cycle of Vs and can be written as diL(t) dt = vs L (2.54a) diL(t) dt = − vc CRL (2.54b) when both of the switches are off, regardless of the positive or negative cycle of Vs, the equation governing the states are the same and can be written as diL(t) dt = vs L − vc L (2.55a) dvc(t) dt = iL C − vc CRL (2.55b) In the same way as showed previously, these equations, (2.54) and (2.55), can be written into a one state state space equation using state space averaging tech- nique[35] and gives the averaged large signal model of the bridgeless PFC as 27 2. Theory [ diL(t) dt dvc dt ] = [ 0 −1−d L d−1 C − 1 CRL ] [ iL vc ] + [ 1 L 0 ] [ vs d ] (2.56) The large signal model of the bridgeless PFC, (2.56), can be liberalized into a steady state operating value by introducing small signal perturbations into the large signal model state values, i.e. replacing iL, vs, vo, and d by steady state variables and a small signal perturbation where iL=IL+îL, vs= Vs+v̂s, vc=Vc+v̂c, and d=D+d̂. Then removing the multiplication of the perturbations and steady state values, it is possible to derive the following small signal model of the bridgeless PFC.[ ˙̂iL ˙̂vc ] = [ 0 −1−D L 1−D C − 1 CRL ] [ îL v̂c ] + [ 1 L Vs L(1−D) 0 − Vs (1−D)CRL ] [ v̂s d̂ ] (2.57) Equation (2.57) represents the small signal model of the bridgeless PFC and the current to duty cycle transfer function can be derived as Gi(s) = îL d̂ = 2Vs + VsRLCs RLLC(1−D)s2 + L(1−D)s+RL(1−D)3 , in canonical form Gi(s) = Vs(2 + sCRL) RL(1−D)3 1 s2 LC (1−D)2 + s L RL(1−D)2+1 (2.58) and the output voltage/capacitor voltage to inductor current transfer function can be derived in same way to get Gv(s) = v̂o îL = Vs 2Vc 1 2VcRLCs+ 1 (2.59) 2.6 Overview on isolated DC-DC converter topolo- gies This DC/DC stage comes after the PFC converter i.e. the outputs of the PFC stage are connected to the inputs of the DC/DC converter. There are many factors that drive to select a suitable topology for a power supply. Some of the important factors are output power level, efficiency, power density, isolation, cost (related to number of power devices), input voltage range and output voltage. Some of the basic topologies that are usually used for isolated DC/DC power con- verters can be listed from lower to higher power application as flyback, forward, push-pull, half-bridge LLC and full-bridge LLC resonant and phase shifted full- bridge converters [36]. The most common topologies among many available resonant converter topologies 28 2. Theory are series resonant converter (SRC), parallel resonant converter (PRC)and LLC res- onant converter. In all the resonant topologies, the working principle is essentially the same. Series resonant converter (SRC) In series resonant converter, the tank circuit is a series connection of one inductor and one capacitor. The tank circuit is connected in series with the load. The fact that, an SRC works as a voltage divider between the resonant circuit and the load, the output voltage regulation is difficult at light or no load for this converter[37].For this converter, the maximum DC gain is 1 and this happens at the resonant frequency where the resonant tank impedance is minimum. Due to its insufficient capability of output voltage regulation and high circulating current at higher switching frequency, this converter is not a good choice for telecom application[38]. Parallel resonant converter (PRC) In a parallel resonant converter, the resonant circuit (one capacitor and inductor connected in parallel) is connected in parallel with the load and this acts as a band stop filter. This converter has better voltage regulation as compared to SRC but larger amount of circulating current requirement as the input voltage increases. There converter topology difficult to apply for applications which need smaller size components and large load variations. Some of the high efficiency resonant converter topologies for the intended application are shown in Table 2.2. Only LLC resonant topology of these isolated type will be discussed in this chapter while the other topologies are deemed to be not suitable for this study. Table 2.2: High Efficiency resonant converters No Topology Feature Power(W) Peak Eff.(%) Ref. 1 Series resonant converter (SRC) Phase shifted, Diode rectification 2000 95.6 [39] 2 Half bridge LLC Diode rectification 350 96.3 [40] SR rectification 600 97.8 [41] Uses GaN switches 1000 97.6 [42] 3 Full bridge LLC Phase shifted, SR rectification 1000 97.6 [43] Uses GaN 3000 98.4 [44] 4 Interleaved half bridge SR rectification 2700 98 [45] 5 Hybrid full bridge-half bridge Diode rectification 3700 98.3 [46] 2.7 LLC resonant converters Nowadays, LLC resonant converters are receiving much attention because of their potential to achieve both higher switching frequencies and higher efficiency. How- ever, the fact that LLC resonant converters are frequency controlled brings more 29 2. Theory challenges in their design as compared to pulse width modulated converters. Essen- tially, all the LLC resonant circuit contains the following basic function blocks: • Switching bridge • LLC tank • Transformer and rectifier circuit • Output filter capacitor The first function block which is the switching bridge, generates a square wave to excite the resonant tank section. The LLC resonant tank block, has the role to generate a resonant sinusoidal current which will get scaled by the transformer and rectified by the rectifier circuit. The fourth block, which is the output section of the circuit contains an output capacitor to filter the rectified sinusoidal current and produces a DC output voltage. The three LLC resonant topologies selected for further discussion are half bridge, full bridge and interleaved half bridge resonant converters, and their mode of oper- ations are explained as follows. Operating modes Depending on the load conditions and input voltage, the operation of the LLC res- onant converter can be seen in three modes. The operating modes of the LLC resonant converter is based on the relationship between the switching frequency, fs, and series resonant frequency, fo. Below resonance, when the switching frequency is below the series resonant fre- quency. In this mode of operation, the converter works in boost mode. Figure 2.21 shows the current wave forms for frequencies below resonant frequency. Between times t1 and t2 the resonant current and the magnetizing current are equal, and no energy is delivered to the load at this time. In this time interval, drain to source capacitance of the primary MOSFET switches helps to discharge the magnetizing current to achieve zero voltage switching. In this operating mode, the magnitude of the resonant current is high and so is the conduction loss. Figure 2.21: When witching frequency is below resonance frequency 30 2. Theory At resonant frequency, when the switching frequency is the same as the series resonant frequency. The input voltage is at its nominal value and the transfer function of the resonant network is not sensitive to load variation. In this mode of operation, the impedance of the resonant tank is minimum, and the converter achieves its highest efficiency. Figure 2.22 shows the tank current wave forms at resonant frequency. Figure 2.22: When witching frequency is equal to resonance frequency Above resonance, when the switching frequency is above the series resonant fre- quency. The magnetizing inductance, Lm, is clamped by the out voltage and it doesn’t participate in the resonance. In this mode of operation, the converter works in buck mode depending on the resonant tank component values. Figure 2.23 shows the tank current wave forms at resonant frequency. Figure 2.23: When witching frequency is above resonance frequency 31 2. Theory 2.7.1 Half-bridge LLC resonant converter Due to its simple structure and capability to achieve soft switching over the entire load range the half bridge LLC resonant converter is commonly used in medium power applications. It has also an advantage of a smaller number of switches in the current flowing path which results in less conduction loss as compared to the full bridge converter. Figure 2.24 shows a typical half bridge LLC resonant converter circuit configuration. Figure 2.24: Half bridge LLC resonant converter 2.7.2 Full-bridge LLC resonant converter This topology is basically the same with half bridge LLC resonant converter except there are four semiconductor devices in the switching bridge. The switching bridge generates a periodical square wave which varies between Vin and −Vin. For the same power level, the current in the primary side of the circuit is reduced as compared to half bridge LLC resonant converter. Therefore, the conduction loss of full bridge is less than the half bridge LLC resonant converter. Similar to half bridge LLC resonant converter, the output capacitance, Coss, of the MOSFET switches in full bridge LLC resonant converter should be fully charged and discharged to achieve zero voltage switching. Thus, sufficient current through the MOSFET during the dead time, td, is required[47]. Figure 2.25: Full bridge LLC resonant converter 2.7.3 Interleaved half bridge LLC converter The Parallel-configuration of LLC resonant converter is a good way to increase the output power rating. The output current and voltage ripple can be reduced 32 2. Theory by introducing an interleaved operation between the two half bridge LLC resonant converters connected in parallel. This helps to achieve higher efficiency[48]. With this topology, high efficiency can reach up to 98% around 2kW output power [45]. The output current from the rectifier switches of the two half bridge LLC is summed up at the output side. As such, the filter capacitor ripple current magnitude is then reduced, which will lead to higher efficiency. Introducing a 90° phase shift between the two legs of the two parallel connected half bridge LLC converters, is a good way to effectively reduce the magnitude of the filter capacitor ripple current. Figure 2.26 shows the circuit configuration of interleaved half bridge LLC resonant converter. Figure 2.26: Interleaved LLC half bridge resonant converter 2.8 Losses and component sizing of LLC stage The power loss in the resonant converter is mainly from conduction losses, copper losses, switching losses of MOSFETs, and transformer core loss. The loss model of each component in the half bridge resonant converter is shown in Figure 2.27. Figure 2.27: Conduction loss model of the LLC resonant converter 33 2. Theory 2.8.1 MOSFETs The selection of the primary side MOSFETs is critical in the LLC converter. The output capacitance of the MOSFETs needs to be low with less focus on the MOS- FET on resistance, as for the total loss of the converter is more advantageous to have a low output capacitance, which will result in a lower energy needed to achieve ZVS. With low MOSFET output capacitance, the value of the magnetizing inductance in the transformer can be made to be high to have low circulating current which will reduce the conduction loss and improve the efficiency. As can be seen from Figure 2.28, during the dead time interval, tdead, the magnetiz- ing current and the resonant current are equal, which indicates that the magnetizing current, Im, circulates through the drain to source capacitances, Cds1 and Cds2 shown in Figure 2.27. To ensure ZVS, there has to be sufficient inductive energy that can charge and dis- charge the two capacitance’s. The dead time, tdead, that can ensure this requirement can then be calculated as: 1 2(Lm + Lr)I2 mpeak ≥ 1 2(2 Ceq)V 2 in (2.60a) tdead ≥ 16 Ceqfs Lm (2.60b) where Ceq is the drain to source capacitance of each MOSFET with some parasitic capacitance’s added to it and fs is the switching frequency. Figure 2.28: ZVS timing for LLC resonant circuit. As can be seen from the wave form in Figure 2.28, the magnetizing inductance 34 2. Theory current,im can be approximated to be an ideal triangle and it can be expressed as: im =  n Vo Lm (t− Ts 4 ) + isec n , 0 ≤ t < Ts 2 n Vo Lm Ts 4 − n Vo Lm (t− Ts 2 )− isec n , Ts2 ≤ t < Ts (2.61) where Ts, fo, isec and n represent the switching period, resonant frequency, current through the secondary MOSFETs and turns ratio of transformer respectively. For the secondary side MOSFETs, the value of the MOSFET on resistance is more important than the output capacitance, but with the requirement that those are also easy to drive, low gate capacitance. The conduction loss associated with each component can be calculated based on the loss model shown in Figure 2.27. The switching loss of the LLC resonant converter comes mainly from the turn-off switching action. As the LLC resonant converter achieves ZVS, the MOSFET’s turn-on action does not contribute to the switching loss. Therefore, the loss calculation is based on the switching transition waveform shown in Figure 2.29. The loss associated with the MOSFET on resistance can be given by Prdson = I2 Lrms rds(on) (2.62) The gate driving loss of each MOSFET is given by Pgate = 1 2CgsV 2 gsfs (2.63) where Vgs and Cgs are the driving signal voltage level and gate to source capacitance respectively. The body diode loss of each MOSFET is given by Pbody = Vbf [n Vo Lm (1 4 1 fs − tdis)] tbody(on) fs (2.64) where tdis, tbody(on) are the discharge time of drain to source capacitance and con- duction time of a body diode. During turn-off transition the rising voltage across the MOSFET and magnetizing current can be assumed to be linear[49]. The drain to source voltage and current can then be expressed as vds(t) = Vds(on) + Vin − Vds(on) tdis t (2.65) ids(t) = n Vo Lm 1 4 fs (1− t tdis ) (2.66) The turn-off loss of each MOSFET is given by Ptoff = fs ∫ tdis 0 vds(t)ids(t)dt = n Vo tdis (Vin + 2Vds(on)) 24Lm (2.67) 35 2. Theory Figure 2.29: Switching transition of LLC resonant converter 2.8.2 Resonant tank inductor and capacitor ESR losses As can be seen from the current waveforms in figure ??, the rms value of the current through the resonant tank is close to that of MOSFET current. The loss in the resonant tank can then be calculated as Ptank = I2 Lrms (rLr + rCr) (2.68) 2.8.3 Transformer To calculate the the losses in a transformer, both core related losses and winding losses are considered. The transformer primary winding loss is given by Ppri = I2 Lrms rpri (2.69) The transformer secondary conduction loss is Psec = I2 sec rms rsec (2.70) The total conduction loss of the transformer is given by Pcu = Ppri + Psec (2.71) The transformer core loss is given by Ptf = Kh B n ac f m s Mcore (2.72) where Bac is the magnetic field strength in Tesla, Mcore is the mass of the core material in kilogram, n and m depend on the material and operating frequency range. The total loss in the transformer can then be given as Pcu = Pcu + Ptf (2.73) 36 2. Theory 2.8.4 Output capacitor The output capacitor power loss is caused by the equivalent series resistance of the output capacitor, rco, as shown in Figure 2.27. This capacitor power loss can be given as Prco = I2 Corms rco (2.74) where ICorms is the RMS current through the output capacitor. Depending on the ripple current magnitude through the capacitor, parallel connec- tion of the output capacitors can be used to reduce the output capacitor loss. 2.8.5 Small signal model of LLC resonant converter Unlike for pulse width modulation (PWM) converters where an averaging model- ing technique can be used, for the LLC resonant converters a different modeling technique is used which is called Extended Describing Function (EDF). With the EDF technique, the small and large signal modeling of LLC resonant converters are derived in [50] as follows. Figure 2.30: Non-linear equivalent circuit of LLC resonant converter The non-linear state equations of the LLC converter in Figure 2.30 is given by vab = Lr dir dt + vCr + Lm dim dt (2.75a) Lm dim dt = sgn(ir − im)vo (2.75b) ir = Cr dvCr dt (2.75c) Co dVco dt (1 + r R ) + vco 1 R = |ir − im|+ io (2.75d) 37 2. Theory vo = r.Ri r +Ri (|ir − im|+ io) + R R + r vco (2.75e) ig = 1 T ∫ T 0 ir vab vg d(t) (2.75f) where ir, im, vCr, vco are state variables and vo and ig are output variables. Approximating the resonant currents and voltages with their fundamental harmon- ics: ir = irs(t)sin(wst) + irc(t)cos(wst) (2.76a) im = ims(t)sin(wst) + imc(t)cos(wst) (2.76b) vCr = vCrs(t)sin(wst) + vCrc(t)cos(wst) (2.76c) Extended Describing function The corresponding EDFs for the non linear equations are derived in [50] and obtained as: f1(vg, d) = 4 π sin(πd)vg (2.77a) f2(irs − ims, vco) = 4 π irs − ims ip vco (2.77b) f3(irc − imc, vco) = 4 π irc − imc ip vco (2.77c) f4(irs − ims, irc − imc) = 2 π ip (2.77d) f5(irs, d) = 2 π ip (2.77e) where ip is ip = √ (irs − ims)2 + (irc − imc)2 (2.78a) Where d is the duty cycle, set to a fixed value. Harmonic balance The frequency of the small signal perturbation is much lower than the switching frequency and the converter can be considered to be in steady state operation. (2.79)can be found by substituting (2.76) to(2.79) into (2.75) and rearranging the 38 2. Theory coefficients of the sine, and cosine terms, Lr( dirs dt − wsirc) + vCrs + Lm(dims dt −−wsimc = 4 π sin(πd)vg (2.79a) Lr( dirc dt + wsirs) + vCrc + Lm(dimc dt + wsims) = 0 (2.79b) Lm(dims dt − wsimc) = 4 π irs − ims ip vco (2.79c) Lm(dimc dt − wsims) = 4 π . irc − imc ip vco (2.79d) Cr( dvCrs dt − wsvCrc) = irs (2.79e) Cr( dvCrc dt − wsvCrs) = irc (2.79f) (1 + r R )Co dvco dt + 1 Ri Vco = 2 π ip + io (2.79g) vo = r.R r +R ( 2 π ip + io) + R r +R vco (2.79h) ig = 2 π irssin(πd) (2.79i) In steady state operation the derivatives of the constant value state variables in (2.75) is zero. Perturbation and linearization By adding a small perturbation signal to the variables as vg=vg+v̂g, io=0+îo, d=D+d̂, ωs = ωs + ω̂s and linearizing the equations, the small signal model of LLC converter can be represented as shown in Figure 2.31 [51]. Figure 2.31: Small signal model of LLC resonant converter For the switching frequency greater than or equal to the series resonant frequency, 39 2. Theory the variables in the small signal model circuit is derived in [51] as Gd = 2Vg π Ln wo 1 Re  1 wn ( 1 w2 n − w2 n)(π2 8 QLn)2 − (Ln + 1− 1 w2 n )( 2 w3 n )[√ (Ln + 1− 1 w2 n )2 + ( 1 wn − wn)π2 8 QLn)2) ]3 + 2 L2 n ) (2.80a) Gv = 1 π Xeq√ X2 eq +R2 eq (2.80b) Kd = 4Vg π 1 woLn (2.80c) Kv = 4 π2 VgLnwn Req Ln + 1− 1 w2 n√ (Ln + 1− 1 w2 n )2 + (( 1 wn − wn)π2 8 QLn)2 (2.80d) Le = (1 + 1 w2 n)Lr (2.80e) Re = LeXeqws − wo Req (2.80f) Ce = 1 (ws − wo)2 (2.80g) Req = 8 π2n 2RL (2.80h) Xeq = wsLr − 1 wsCr (2.80i) Ln = Lm Lr (2.80j) From (2.80) the transfer function of the LLC resonant converter for the switching frequency greater than the series resonant frequency can then be expressed as V̂o(s) ω̂(s) = Gd X2 eq +R2 eq (s2Le + sLeReq +X2 eq)(1 +RLCos) +Req(sLe +Req) (2.81a) Q = √ Lr Cr n2.RL (2.81b) For the switching frequency less than the series resonant frequency, the variables in 40 2. Theory the small signal model circuit is derived in [51] as Gd = 2Vg π Ln wo 1 Re  1 wn ( 1 w2 n − w2 n)(π2 8 QLn)2 − (Ln + 1− 1 w2 n )( 2 w3 n )[√ (Ln + 1− 1 w2 n )2 + (( 1 wn − wn)π2 8 QLn)) ]3 + 2 L2 n ) (2.82a) Gv = 1 π Xeq√ X2 eq +R2 eq (2.82b) Kd = 2Vg π Ln wo [ ( 1 w2 n − w2 n)(π2 8 QLn)2 − (Ln + 1− 1 w2 n )( 2 w2 n ) ] 1 wn . 1 sin(wn π2 ) + ( −π 2 cos(wn π2 ) sin2(wn π2 ) ) √ (Ln + 1− 1 w2 n )2 + (( 1 wn − wn)π2 8 QLn)2 (2.82c) Kv = 2 π Ln sin(wn π2 ) 1√ (Ln + 1− 1 w2 n )2 + (( 1 wn − wn)π2 8 QLn 1 sin(wn π2 ))2 (2.82d) Le = (1 + 1 w2 n)Lr + (1− wn)Lm (2.82e) Re = 0 (2.82f) Ce = 1 (ws − wo)2 (2.82g) Req = 8 π2n 2RL (2.82h) Xeq = wsLr − 1 wsCr (2.82i) Ln = Lm Lr (2.82j) From (2.82) the transfer function of the LLC resonant converter for the switching frequency less than the series resonant frequency can then be expressed as V̂o(s) ω̂(s) = Gd 1 1 + s Qpwp + s2 w2 p (2.83a) Qp = 8n π2RL √ Co Le (2.83b) wp = √√√√ 1 Le π2 8n2Co (2.83c) 41 2. Theory 42 3 Method 3.1 Modeling of the selected AC/DC converter topologies In order to model the AC/DC converter topology we can model the PFC stage and LLC stage separately. Some of the topologies of the PFC stage and LLC stage may not be compatible or practical which will be discussed later. Since the efficiency of the combined stage will be the multiplication of each individual topology, for a certain power range, if both stages achieve a higher efficiency, then the combined efficiency will be higher. The voltage inputs of the AC/DC converter are 85-275V with 47 to 63Hz of frequency and the output is a DC voltage of 48V. The PFC and LLC converters topologies are going to studied separately and in the next chapter the loss distribution plots will be presented separately, and the efficiency of the cascaded topologies are presented together. Finally, based on analytical and simulation results, the topology compari- son in terms of efficiency, cost and performance the topology selection will be made for around 500W, 1kW and around 2kW of power levels. 3.2 Modeling of the PFC stage Many topologies can be implemented as a front-end rectifier. Based on the litera- ture study, active boost, interleaved and bridgeless PFC topologies are going to be modeled and will be studied for further analysis in performance, efficiency and cost perspectives. Other topologies were deemed not suitable in this study. As the efficiency of each topology depends on the type of components chosen, the same type of components that can function for the given power ranges should be chosen. This methodology will make it easier to understand the power loss of each component implemented in different topology and will simplify the efficiency com- parison. The output of the front-end PFC will then be the input to the LLC con- verter. The components chosen in this study can function properly for specifications listed in Table 3.1. Some of the loss calculations might consider a 230V input and 50Hz of frequency as a way of design. The input voltage range and frequency are chosen base on telecom requirement or universal input voltage range. The typical output 43 3. Method of the PFC stage is 400V, but the LLC design consider a certain voltage range as its input. The output power is the range at which this study is based and the switching frequency is chosen considering switching losses and size of passive devices. Table 3.1 summarizes the input and output specification of the PFC stage. Table 3.1: Input and output specifications of PFC stage Input Voltage 85-275 V Output voltage 400 V Grid Frequency 47-63 Hz Output power 500-2000 W Switching frequency 100 kHz 3.2.1 Diode bridge rectifier The diode bridge for active boost and interleaved PFC topologies should be selected in such a way that it can handle the maximum current through it, when the voltage is minimum and the maximum voltage across its terminals. Furthermore, the on time resistance and the voltage drop across the diode that made up the bridge rectifiers should be considered. For minimum voltage input, 85V RMS, and maximum output power, 2000w and assuming converter efficiency of 98%, the average current through the diode can be calculated as Iin,avg = 2 √ 2 π Po,max Vin,minη = 0.9 2000 85 · 0.98 = 21.6A, The average current capability of the bridge rectifier should then be at least 22A. Since the output voltage is 400, the bridge rectifier should block at least 400V. The selected diode bridge can block 560V of reverse voltage and has 25A average current flow capability which is suitable for simulation and loss analysis study. The power loss in the diode bridge can be calculated using (2.5) and the datasheet information. For an output power of 1kW, assuming efficiency of 98%, and input of 230V RMS with 50Hz, the average and the RMS current will be 4A and 4.44A respectively. The forward voltage drop, Vf of the bridge rectifier per diode is around 0.9 around 4A and the forward resistance is around 0.025Ω at 26◦C. Due to natural turn off the diodes in the bridge have a negligible reverse recovery losses. Pdiode,c = 2 · (VfIav +RI2 rms) = 8.2W. The bridge rectifier loss can be done for different power rating and voltage input using the same procedure. For bridgeless PFC, the average and RMS current are the same as active boost and interleaved PFC. But, as discussed in the previous chapter, the current return path is through body diode of one of the MOSFETs and through the slow diode. The loss due to the body diode will be discussed in MOSFET losses MOSFET losses. If roughly half of the current passes through the slow diode then, the power loss is Pslowdiode,c = VfIav +RI2 rms = 1.93W. 44 3. Method 3.2.2 Boost inductor The inductor size mainly depends on the amount of ripple current allowed, and rip- ple current depends on the type of conduction mode of the PFC. Considering CCM, usually 15% to 40% of ripple current is considered for boost inductor design. In some designs, a small capacitor is connected right after the diode bridge to decrease the ripple current in the inductor[7]. Allowing 20% current ripple, the minimum inductor size for active boost and in- terleaved PFC can be calculated using (2.11) and for bridgeless using (2.12) which basically results in the same minimum inductor size of 257 µH. In the simulation a standard value of 300 µH is used in the simulation. The core selection should be in such a way that the number of copper wire turn should result in the same inductance value. The core selection can be made through different methods. For this study, the core is selected from the supplier’s, Magnetic- inc®, catalog based on Li2L, where L is inductance value and IL peak inductor current. A powdered core of type Kool Mu with part number 0077071A7HT15 is selected. Table 3.2 shows the properties of the selected core. Table 3.2: Main properties of selected core material Inductance nH/T2 OD Length [mm] Le Path Length [mm] Ae Cross Section [mm2] Ve Volume [mm3] 80 33.66 81 86 7000 The number of turns to get 300µH can be calculated as N = √ L Inductance this yields a turn ratio of around 61. The core loss can be determined from two curve fit equations from the core suppliers guide. The first one determines the maximum and minimum magnetic field strength, H, from the minimum and maximum currents through the inductor using H = 4πNIL Le (3.1) where N is number of turns, IL is inductor current and Le is the path length. The second curve fit equation uses the magnetic the power density based on average magnetic flux density, B, of around 0.05T. This will give a power loss of 159.8mW per cubic centimeter at 1kW of power level. Multiplying this with the volume of the core Ve gives a core loss of around 1.12W. Other core materials like 3C95 are also evaluated using Steinmetz equation to give nearly the same results. The copper loss of an inductor depends on the type of wire used. By choosing the type of inductor wire and determining its length, it is possible to determine its direct current resistance, DCR. 45 3. Method RDC = MLTNRL (3.2) where MLT is the mean length of turn, N is the number of turns and RL is the resistance per unit length of the copper wire selected. AWG 18 wire is selected and it has 0.021 mΩ/m, the mean length of turn is nearly 6.3 cm/turn, which gives an RDC of 80 mΩ. In active boost and bridgeless PFC, the RMS current through the inductor is the same as the input RMS current which can be express as IL,rms = Pout ηVin (3.3) For 1kW of power the conduction losses of the inductor in active boost and bridgeless PFC will be PL,cond = RDCIL,rms 2 = 1.57W For interleaved PFC the input RMS current will be channeled into two separate legs which basically reduces the inductor’s conduction loss by half. 3.2.3 MOSFET The MOSFET losses are mainly switching and conduction losses. The conduction losses can be found by first calculating the RMS current through the MOSFET. For active boost and bridgeless PFC, which can be found by evaluating (2.16), for 1kW, of power which gives 2.64A. For interleaved PFC it will be 1.32A. The conduction loss of the active boost and bridgeless PFC gives 1.32W. The switching frequency for active boost and bridgeless PFC is the same as sys- tem/converter frequency, 100kHz. For interleaved PFC, if the system frequency is assumed to be 100kHz, then the effective switching frequency will be doubled as the switches are 180◦ phase shifted from each other. To keep the same effective frequency of the switch, the system frequency of the interleaved PFC is 50kHz. Consequently, the switching losses remain the same in all the three PFC topologies while the conduction loss will be half in interleaved PFC and additional body diode losses are present in bridgeless PFC. The turn on and turn off switching losses, can be evaluated using (2.20) and (2.23) respectively and the parameters can be found from the datasheet. For 1kW of power, the total switching loss for all three PFCs topologies gives 3.25W. The total loss comprised of switching loss, conduction loss, gate loss and body diode loss associated with the MOSFET gives 5W for active boost. For interleaved it is found to be 3.97W. For bridgeless PFC, since the return current flows though one slow diode and one body diode of the MOSFET, the MOSFET losses are 6.44W, which are higher than the MOSFET losses of active boost PFC. 46 3. Method 3.2.4 Boost diode The boost diode selection is also critical since its losses also impose additional losses into the MOSFET and output capacitor. Taking this into consideration, a low re- verse recovery silicon carbide/SiC, boost diode is selected. The selected boost diode has a reverse blocking capability of 650V, and total capacitive charge, and voltage drop of 1.5V at 8A average current. The total losses, can then be calculated using (2.26) and (2.5) to get 4.15W for the active boost and bridgeless PFCs. For the interleaved PFC, the switching losses remain the same and the conduction losses will be roughly half. Which gives a total power loss of 2.37W. 3.2.5 Output Capacitor The size of the capacitor is calculated based on the equation explained in the theory chapter. The size of the capacitor is greatly affected by the power rating. For 1kW power based on hold up time requirement, using (2.27) of 20ms, the capacitor size becomes 490 µF and based on the ripple voltage requirement, using (2.28), consid- ering 3% of voltage ripple the size becomes 497.4µF. The largest should be chosen as the minimum size of the capacitor. A 330µF Aluminum electrolyte capacitor is selected from Vishay. Two of these capacitors shall be connected up to 1kW and three of them shall be connected in parallel for 2kW. Once the type of capacitor is selected, its losses can be calculated using (2.30). Connecting the capacitor in parallel reduces the capacitor loss by half and increases thermal performance. For 1kW, the capacitor power loss for the active boost and the bridgeless PFC is around 0.605W and for interleaved topology it becomes 0.340W. The difference is due to the reduction of RMS current in interleaved PFC. Power losses from 200W to 2200W levels are computed using the same method as explained above. Table 3.3 summarizes the selected components in all the three PFC topologies. At 2kW of power the number of capacitors shall be increased to three in all topologies. Table 3.3: Quantity of components used Components Part no. Active boost Interleaved Bridgeless Diode bridge GBJ2508 4 4 2 MOSFET R6020PNJ 1 2 2 Boost diode FFSB0865A 1 2 2 Capacitor MAL225957331E3 2 2 2 Inductor/core 0077071A7HT15 1 2 2 Total no. of components 9 12 10 The diode bridges in the bridgeless PFC are slow diodes and are not used for rectification purpose. 47 3. Method 3.2.6 Simulation model of PFC The simulation model used for determining the losses was developed in LTspice using the devices mention in the circuit components in Table 3.3. Some of the component’s model were downloaded from the suppliers and some of them can be found in LTspice database. For the inductor, the LTspice model could not be found and the DC resistance calculated above were inserted into the inductor’s default model and similarly, the ESR was inserted into the capacitors data in the LTspice default component model. 3.3 Modeling of LLC resonant converter The input voltage of the LLC converter is the output of PFC stage which is 400V. Even if the output voltage of the PFC is assumed to be constant because of unknown reasons the voltage might fluctuate, so to insure safe operating area of the LLC stage an input range of 370-430V is considered to model the converter. Table 3.4: Specification and design parameters specification and Parameters Value Unit DC bus voltage range Vin 370-430 V Output voltage Vout 48 V Rated output power Po,rated 500-2000 W To design an output voltage regulated variable energy transfer converter, a mathe- matical relationship between input and output voltage is a must. The LLC resonant converter operates in the vicinity of a series resonance which indicates that the cir- culating current can be assumed to be a pure sinusoidal of a single frequency. The analysis is based on the First Harmonic Approximation method, in which only the fundamental harmonic component of the square wave input voltage is consid- ered while ignoring the higher order harmonics to design the resonant converter. As long as the switching frequency is at, or close to, the resonant frequency the result obtained with this method is valid[37]. The voltage transfer function can then be developed with the FHA method, repre- senting the LLC resonant converter with its AC equivalent circuit model as shown in Figure 3.1. All variables are referred to the primary side. 48 3. Method Figure 3.1: AC equivalent model of LLC resonant converter. The RMS voltage on the input side is V1 = √ 2 π Vin (3.4) The RMS voltage on the output referred to the primary side is Vop = 2 √ 2 π Vo (3.5) The RMS output current referred to primary is Iop = π 2 √ 2 1 n Io (3.6) The AC equivalent load resistance can be calculated as Rac = Vop Iop = 8n2 π2 RL (3.7) where n is the turns ratio of the transformer and it is given by n = Vin−nom 2 Vo−nom (3.8) The input to output voltage gain function can be expressed in a normalized format to give a general description of design issues. To do this, inductance ratio, Ln, normalized frequency, fn and quality factor, Q are define as follows: Normalized frequency fn = fsw fo (3.9) inductance ratio Ln = Lm Lr (3.10) 49 3. Method quality factor of series resonant circuit Q = √ Lr/Cr Rac (3.11) The resonant frequency, fo, is calculated as: fo = 1 2π √ LrCr (3.12) The input-output transfer function can then be expressed as Mg = | Lnf 2 n [(Ln + 1)f 2 n − 1] + j[(f 2 n − 1)fnQLn] | (3.13) Depending on the load and gain requirements for a specific application, reasonable values of inductance ratio, Ln and quality factor, Q can be selected. Figure ?? shows how to how to select the value of the inductance ratio depending on our gain requirement. Figure 3.2 shows Mg and Q values for different inductance ratio, Ln. Figure 3.2: Inductance ratio, Ln, selection. There is a trade of between higher and lower inductance ratio, Ln, selection. Higher inductance ratio means higher monetizing inductance, this has an advantage of hav- ing smaller circulating current in the resonant circuit which will help us to have higher efficiency, but this will lead to have low gain. To get the required gain we must go to a relatively low frequency. On the other hand, smaller inductance ratio, Ln, has an advantage of higher boost gain and narrow frequency range. But this will increase the conduction loss, mean- ing at the end, reduce the efficiency. Therefore, an inductance ratio between Ln=4 50 3. Method and Ln=7 is practical and kind of optimum value to choose in this design. A plot of voltage gain with respect to normalized frequency shown in Figure 3.3 is one good way to explain how the voltage gain behaves for different factors such as LLC tank parameters, switching frequency and load. A family of curves are presented in the same figure to show how the gain curve can be reshaped by changing Ln and Q. With the proper selection of the LLC tank parameters, it is possible to make the impedance of the tank inductive. As such, the primary side MOSFET zero voltage switching (ZVS) can be achieved over the complete range of operation. (a) Ln=2 (b) Ln=5 (c) Ln=10 (d) Ln=20 Figure 3.3: Voltage gain vs normalized frequency at different inductance ratio values. According to the different values of design parameters, Ln = 5 and Q = 0.4 is chosen for this design and the voltage gain curve of full bridge LLC resonant converter is shown in Figure 3.4. The voltage gain curve of half bridge is done essentially the same way except the value of the transformer ratio is different. 51 3. Method Figure 3.4: Voltage gain curve of full bridge LLC resonant converter The normalized frequency, fn. at the maximum gain cross or Mgmax in Figure 3.3 decides the minimum switching frequency we can have and fn at the minimum gain cross orMgmin in Figure 3.3 decides the maximum switching frequency we can have. The design parameters are calculated according to the design equations and tabu- lated in Table 3.5 . Table 3.5: Design parameters of LLC resonant converter Parameters Values Half bridge LLC Full bridge LLC Magnetizing inductance, Lm 160µH 350µH Series resonant inductor, Lr 30µH 60µH Series resonant capacitor, Cr 60nF 30nF Transformer turns ratio, n 4.16 8.33 Output capacitor, Co 560µF 560µF Resonant frequency, fo 130 kHz 130 kHz The size of the resonant inductor and capacitor is different for half bridge and full bridge LLC resonant converters. The resonant inductor and capacitor part numbers given in this table are for half bridge LLC resonant converter. However, this difference is considered to be negligible when comparing the number of components. 52 3. Method Table 3.6: Components used in the LLC resonant converter design Components Part no. HB LLC Int. HB LLC FB LLC Primary MOSFET R6020PNJ 2 4 4 Transformer material EQ30-3C94 1 2 1 Secondary MOSFET R6020PNJ 2 4 2 Resonant capacitor C0402C563K7PAC 1 2 1 Resonant inductor DAMT2-26-11 1 2 1 Output capacitor MAL225957331E3 1 1 1 Total no. of components 8 15 10 Int. HB LLC referes to interleaved half bridge LLC converter. 3.3.1 Simulation model of LLC The simulation model used for determining the losses was developed in LTspice with the circuit components in Table 3.6 and circuit parameters in Table 3.5. The MOSFETs used are based on what is available in LT-spice database, they are not the best choice when it comes to MOSFET selection for LLC resonant converters, but they are still fine for topology comparison. One can model or search for other MOSFETs with low turn on resistance and low output capacitor value to have a good loss distribution with reduced power loss in the MOSFETs. Some of the components ESR values are taken from the LTspice and some are calculated and inserted into the inductor’s default model. 53 3. Method 54 4 Results Three front end PFC topologies and three LLC resonant converter topology has been studied for their power loss distribution, efficiency, power density and cost. The analytical loss calculation models where developed and verified with simulation models. The results for the power loss distribution for the PFC stage and LLC stage are presented here, separately, and the efficiency graphs are plotted for the combination of selected PFC and LLC stages. 4.1 Loss distribution of the PFC stage The losses in the converter were calculated using nearly a power factor of one. In order to determine the losses via simulation, the current waveform/the power factor should be acceptable, >0.98. At 230V and 1kW of power, which has a power factor of 0.9882, Figure 4.1 shows the input current and the supply voltage waveforms of this PFC. For the interleaved and bridgeless PFCs, the supply current waveforms can be found in the appendix. Figure 4.1: Current and voltage waveforms of active boost PFC at 1kW The analytical and simulation results for the Active boost PFC show that the loss distribution in the converter is mainly because of the bridge rectifier and the MOS- FET switch as shown in Figure 4.8. This similarity is common for all the three topologies of PFC. The results indicate that, as the load increases, the conduction 55 4. Results losses become dominant especially the bridge losses and the efficiency start to drop after 600W as shown in Figure 4.6. This is due to the reason that the conduction losses in the converter are related to the square of the current through the converter. (a) analytical loss distribution (b) simulation loss distribution Figure 4.2: Loss distribution of the active boost PFC In LTspice, the power loss in a component can easily be found by integrating the voltage and current overlapping areas via built in LTspice functions. This can be done by; one, measuring the voltage across the component and the current through it and integrate the area and two, by holding left Alt key and clicking left mouse key on the component which the power loss is measured. Both methods give the same results and after measuring the power losses in each component a bar graph can be plotted. Figure 4.3 shows the quantitative power loss of each component in all the three topologies at 500W, via simulation. Figure 4.3: Power loss distribution at 500W The power losses in the active boost PFC are higher since it has more components in the current direction and the interleaved PFC shows a reduced power loss as 56 4. Results compared with the active boost as it has two separate power channel which reduces the conduction losses. The bridgeless PFC has the lowest power loss as it has fewer number of components in the current flowing path. Figure 4.4 shows the power loss distribution at 1kW. The results indicate that re- duction of conduction losses in the MOSFET, inductor and boost diode is now more visible as compared with the results at 500W. Figure 4.4: Power loss distribution at 1kW As the power level increases the conduction losses become more evident and the losses in the active boost PFC becomes much higher as compared with the inter- leaved PFC as shown in Figure 4.5. This excessive power loss in the active boost PFC restricts the usage of this topology for higher power levels. The bridgeless PFC still shows less power losses due to