Design and Simulation of a Microcontroller- Based Class D Power Amplifier for Piezo- electric Actuators in Bone Conduction Hearing Aids Master’s thesis in Biomedical Engineering ALBIN REMNESJÖ BERGSTRAND EMIL JOHANSSON DEPARTMENT OF ELECTRICAL ENGINEERING CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2025 www.chalmers.se www.chalmers.se Master’s thesis 2025 Design and Simulation of a Microcontroller-Based Class D Power Amplifier for Piezoelectric Actuators in Bone Conduction Hearing Aids Albin Remnesjö Bergstrand Emil Johansson Department of Electrical Engineering Division of Communications, Antennas, and Optical Networks Chalmers University of Technology Gothenburg, Sweden 2025 Design and Simulation of a Microcontroller-Based Class D Power Ampli- fier for Piezoelectric Actuators in Bone Conduction Hearing Aids Albin Remnesjö Bergstrand, Emil Johansson © Albin Remnesjö Bergstrand, Emil Johansson, 2025. Supervisor: Armin Azhirnian, Cochlear Examiner: Erik Agrell, Department of Electrical Engineering Master’s Thesis 2025 Department of Electrical Engineering Division of Communications, Antennas, and Optical Networks Chalmers University of Technology SE-412 96 Gothenburg Telephone +46 31 772 1000 Cover: A visual representation of a skull model with a piezoelectric actuator posi- tioned on its side. The actuator symbolizes the core technology of bone conduction and is illustrated transmitting acoustic vibrations in the skull bone, which is repre- sented as musical notes flowing in the background. Typeset in LATEX, template by Kyriaki Antoniadou-Plytaria Printed by Chalmers Reproservice Gothenburg, Sweden 2025 Design and Simulation of a Microcontroller-Based Class D Power Ampli- fier for Piezoelectric Actuators in Bone Conduction Hearing Aids. Albin Remnesjö Bergstrand, Emil Johansson Department of Electrical Engineering Chalmers University of Technology iii Abstract Conventional linear audio power amplifiers have been and continue to be popular in audio applications. In recent years, digital Class D switching power amplifiers have increased in popularity, as the demand for smaller and more efficient electronic devices has surged. Continuous technological advances have further improved audio quality and allowed for smaller and more efficient Class D amplifiers. One audio technology that uses Class D amplifiers is bone conduction hearing aids. These systems generally consist of an extrinsic microphone and sound processor, connected to a percutaneous device with the purpose of generating sound through vibrations to the skull bone. Historically, bone conduction devices have been designed and operated based on electromagnetic principles using electromagnetic actuators. Over time, a more efficient type of actuator is increasing in popularity, one that utilizes the piezoelectric force. Low-voltage Class D amplifiers are often only available in integrated circuits (ICs), which take a long time to develop and can be a bottleneck in the process. This thesis explores an alternative approach by developing a design and simulation framework for a low-voltage Class D power amplifier using discrete components to drive a piezoelectric actuator load. The following approach aims to reduce the development time while showcasing the feasibility of constructing low-voltage Class D power amplifiers utilizing discrete components for piezoelectric actuator loads, achieving performance comparable to integrated solutions. A Class D amplifier, using a H-bridge power stage, with ∆Σ to BD PWM with dead-time control, has been developed in simulation and with PCB design. The amplifier, operating across the audio frequency range (20 Hz to 20 kHz), achieved a peak SNR of 69.32 dB and a THD+N peak of 0.15% when driven with a 0.658 VRMS sinusoidal input with a fundamental frequency of 4410 Hz. A peak apparent efficiency of 86.4% was observed with an input voltage of 2.44 VRMS. Compared to IC designs reported in technical literature and found in commercial products, the results are promising. Thus, the conclusion is that the idea of designing a low-voltage discrete Class D amplifier for piezoelectric hearing aids is deemed viable. Still, its performance could be greatly improved by incorporating gate drivers, a higher-order ∆Σ modulator, and more refined filter designs. Keywords: Bone conduction, hearing aid, piezoelement, sigma Delta, Class D am- plifier iv Acknowledgements Firstly, we would like to express our sincere gratitude to Cochlear Bone Anchored Solutions AB for providing us with the opportunity to conduct our master’s thesis at the company and for their confidence in our abilities. We would like to deeply thank our supervisor at Cochlear, Armin Azhirnian for his invaluable support and knowledge. The project took longer, required more work and effort than expected, and without Armin’s knowledge and encouragement, completing this work would not have been possible. We sincerely thank our supervisor at Chalmers University of Technology, Björn Langborn for his assistance in organizing the report and ad- ministrative assistance, which have been greatly appreciated. We also would like to thank our examiner and Professor Erik Agrell for valuable insight and support when writing and structuring the thesis. Lastly, we send our greatest gratitude to those who have supported us throughout this journey, colleagues, friends, and family, thanking you for your encouragement and belief in us. Albin Remnesjö Bergstrand, Emil Johansson, Gothenburg, 2025 vi List of Acronyms Below is the list of acronyms that have been used throughout this thesis listed in alphabetical order: ACHA Air Conduction Hearing Aid ADC Analog-to-Digital Converter AD PWM 2-level PWM; A indicates the PWM level, D indicates Class D BD PWM 3-level PWM; B indicates the PWM level, D indicates Class D BCH Bone Conduction Hearing BCHA Bone Conduction Hearing Aid BEST Balanced Electromagnetic Separation Transducer BTL Bridge-Tied Load CMOS Complementary Metal Oxide Semiconductor DAC Digital-to-Analog Converter DSP Digital Signal Processing dB Decibel dBFs Decibel relative to Full Scale DevKit Development Kit EM Electromagnetic EV-Kit Evaluation Board FIR Finite Impulse Response IIR Infinite Impulse Response IC Integrated Circuit I2S Integrated Inter-IC Sound Bus LSB Least Significant Bit MCU Microcontroller Unit MOSFET Metal Oxide Semiconductor Field Effect Transistor MSB Most Significant Bit NTF Noise Transfer Function OSR Oversampling Ratio PC Polycarbonate PCB Printed Circuit Board PCM Pulse Code Modulation PDM Pulse Density Modulation PLL Phase-Locked Loop PSD Power Spectral Density viii PWM Pulse Width Modulation RMS Root-Mean-Square SCK Continuous Serial Clock SD Serial Data SINAD Signal-to-Noise and Distortion Ratio SNR Signal-to-Noise Ratio SPL Sound Pressure Level STF Signal Transfer Function THD Total Harmonic Distortion THD+N Total Harmonic Distortion + Noise WS Word Select ∆Σ Delta-Sigma ix Nomenclature Below is the nomenclature of parameters and variables that have been used through- out this thesis. Parameters DF Dissipation factor M Sum iteration number for THD and THD+N q Quantization step size T One period ω Angular frequency, 2πf Variables CP Parasitic capacitor CPZ Capacitance of actuator (PZ = piezo) EC Energy stored in a parasitic capacitor eq Quantization error f0 Fundamental frequency of the sinusoidal input Faudio Input audio frequency fPWM PWM clocking frequency fr Resonance frequency fs Original sampling rate Fs Final sampling rate after oversampling FSW Switching frequency of the amplifier Ig Gate current Îo Output peak current Io,RMS Output RMS current xi Irrm Maximum body-diode reverse-recovery current IQ Quiescent current i(t) Instantaneous output current N Number of bits P0 Power of the fundamental frequency component PBD Body-diode power losses PC Average consumed power in a parasitic capacitance PCL Conduction power losses Pdt Dead time power losses PFILT Power losses in the output filter Pin Input power Ploss Power losses in the amplifier for a resistive load Ploss,adj Total power loss adjusted for the model in this work Pn Power of noise in the bandwidth of interest Po Output power Po,app Apparent output power Preac Reactive power Px Power of harmonics in the bandwidth of interest Prr Reverse-recovery charge power loss PSW Switching power losses Ptrans Transition power loss PQ Quiescent power losses Q Quality factor Q(x) Quantized output Qg Total gate charge q Quantization step size r Exponent of the oversampling rate RDS(on) On-state drain–source resistance tdt Dead-time implemented to avoid Shoot-through current trr Body-diode reverse-recovery time tswitch Switching time (time to charge the MOSFET gate) ttrans Transition time of the MOSFET v(t) Instantaneous output voltage VGS MOSFET Gate-Source voltage xii V 2 i RMS input voltage squared VCP Voltage across a parasitic capacitor V̂i Input peak voltage Vo,RMS RMS output voltage Vn RMS noise voltage within the bandwidth of interest VDD Supply voltage VGS Gate–source voltage Vrail Rail voltage connected to PMOS1 and PMOS2 VSD Body-diode source-to-drain voltage XC Capacitive reactance XL Inductive reactance x Input signal to quantizer σ2 e Average quantization noise power σ2 x Average power of quantized signal |ZF | cos(ϕ) Resistive part of the filter at audio frequency fPWM ϕ Phase shift between current and voltage xiii Contents List of Acronyms viii Nomenclature xi List of Figures xvii List of Tables xx 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Research Gap and Motivation . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Aim and Research Question . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Fundamentals of Audio Amplification in BCHAs 4 2.1 Overview of Digital BCHA Systems . . . . . . . . . . . . . . . . . . . 4 2.2 Vibration Technologies in BCHAs . . . . . . . . . . . . . . . . . . . . 5 2.2.1 Electromagnetic Transducers . . . . . . . . . . . . . . . . . . . 5 2.2.2 Piezoelectric Ceramic Actuators . . . . . . . . . . . . . . . . . 6 2.3 Performance Measures of Audio Amplifiers . . . . . . . . . . . . . . . 6 2.3.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . 7 2.3.3 Distortion Metrics . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.4 Efficiency of Switching Audio Amplifiers with Resistive Loads 8 2.3.4.1 Efficiency of Switching Audio Amplifiers with Piezo- electric loads . . . . . . . . . . . . . . . . . . . . . . 9 2.3.4.2 Power losses in Switching Audio Amplifiers with Piezo- electric Loads . . . . . . . . . . . . . . . . . . . . . . 11 3 The Digital Class D Audio Power Amplifier 14 3.1 Overview of Audio Power Amplifier Classes . . . . . . . . . . . . . . . 14 3.2 Modulation Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . 16 3.3 Class D Power Amplifier Stage . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Series-Resonant Circuits . . . . . . . . . . . . . . . . . . . . . 21 xiv Contents 4 Digital-to-Analog Converters 23 4.1 Decibels Relative to Full Scale . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Nyquist-Rate Digital-to-Analog Converters . . . . . . . . . . . . . . . 23 4.2.1 Quantization in a Nyquist DAC . . . . . . . . . . . . . . . . . 23 4.2.2 Signal-to-Noise Ratio in a Nyquist DAC . . . . . . . . . . . . 25 4.3 Oversampling Converters . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 ∆Σ Digital-to-Analog Converter . . . . . . . . . . . . . . . . 26 5 Digital ∆Σ Modulation 28 5.1 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.1 Upsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.2 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.3 Half-Band FIR Filter . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 First Order ∆Σ Modulator Feedback Loop . . . . . . . . . . . . . . . 31 5.3 Higher Order ∆Σ Modulator Feedback Loops . . . . . . . . . . . . . 32 6 Method 34 6.1 Selection of Microcontroller . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 Design and Simulation in MATLAB . . . . . . . . . . . . . . . . . . . 35 6.2.1 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 Design and Implementation of the ∆Σ modulator . . . . . . . 36 6.2.3 Conversion of ∆Σ to BD PWM . . . . . . . . . . . . . . . . . 38 6.2.4 Performance Analysis of BD PWM . . . . . . . . . . . . . . . 39 6.2.5 Implementation of Dead Time Control in BD PWM . . . . . . 43 6.2.6 Dither Noise Generation in Quiescent Power Measurement . . 44 6.3 Design and Simulation of the Class D Power Amplifier in LTspice . . 45 6.4 Design of the Output Stage PCB . . . . . . . . . . . . . . . . . . . . 47 6.5 Microcontroller Implementation . . . . . . . . . . . . . . . . . . . . . 48 6.5.1 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5.2 I2s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5.3 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7 Results 50 7.1 Performance of the ∆Σ modulator . . . . . . . . . . . . . . . . . . . 50 7.2 Analysis of ∆Σ to BD PWM Conversion . . . . . . . . . . . . . . . . 51 7.3 Dead-Time Control Optimization and Shoot-Through Prevention . . 52 7.4 PCB Design and Prototype . . . . . . . . . . . . . . . . . . . . . . . 54 7.5 Frequency Domain Analysis: SNR, THD, and THD+N . . . . . . . . 55 7.6 Power Consumption and Efficiency . . . . . . . . . . . . . . . . . . . 58 8 Discussion 60 8.1 Frequency analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2 Efficiency & Power consumption . . . . . . . . . . . . . . . . . . . . . 63 9 Conclusion 64 9.1 Proposed System Overview for Future Work . . . . . . . . . . . . . . 65 A LTspice Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I xv Contents B MATLAB SNRTest Function . . . . . . . . . . . . . . . . . . . . . . . II C MATLAB SINADTest Function . . . . . . . . . . . . . . . . . . . . . VI D MATLAB Function for Halfband Design . . . . . . . . . . . . . . . . IX E MATLAB Errorcreation Function . . . . . . . . . . . . . . . . . . . . XI F MATLAB Findindex Function . . . . . . . . . . . . . . . . . . . . . XII G MATLAB Usampling Function . . . . . . . . . . . . . . . . . . . . . XIII H MATLAB ∆Σ Modulator Function . . . . . . . . . . . . . . . . . . . XVI I MATLAB Function for Resampling Gate signals . . . . . . . . . . . XVIII xvi List of Figures 2.1 A generic digital BCHA system. . . . . . . . . . . . . . . . . . . . . . 4 2.2 (a) Cross-sectional view of the B71 BC transducer. (b) Cross-sectional view of the B81 or Balanced Electromagnetic Transducer (BEST). Both images from [14]. Allowed by author to use. . . . . . . . . . . . 5 2.3 Structure of a generic piezo actuator . . . . . . . . . . . . . . . . . . 6 2.4 Output voltage and current over the piezoelectric actuator in a switch- ing audio amplifier, illustrating the 90◦ phase shift. . . . . . . . . . . 9 2.5 Power triangle, showing the relationship between active power, reac- tive power, and apparent power. . . . . . . . . . . . . . . . . . . . . . 10 2.6 Output current trough the piezoelectric actuator together with the ideal audio current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Schematic of an H-bridge Class D amplifier with high-side PMOS and low-side NMOS, driving a speaker through a low-pass filter. . . . . . 15 3.2 (a) A-side and, (b) B-side PWM signal, and (c) the resulting BD modulated output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 (a)First transition mode of the switches producing a positive output, and (b) second transition mode which gives a negative output. . . . 20 3.4 Different switching modes that generate no output, therefore zero- modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Unwanted switching modes that cause short circuits, which dead time control is designed to prevent. . . . . . . . . . . . . . . . . . . . . . . 21 3.6 Series resonance circuit showing an RLC circuit consisting of an AC voltage source, a resistor, an inductor, and capacitor [32]. . . . . . . 21 3.7 Impedance versus frequency for capacitance and inductance, and high- lighting the resonance frequency. . . . . . . . . . . . . . . . . . . . . . 22 4.1 PDF and PSD of the quantization error in an ideal Nyquist-rate DAC. 24 4.2 General block schematic of a first order ∆Σ DAC. . . . . . . . . . . . 27 4.3 Comparison of the PSD of quantization noise for Nyquist sampling, oversampling, and noise-shaped signals. . . . . . . . . . . . . . . . . . 27 5.1 Frequency response of an ideal half-band FIR filter compared with compared with practical implementations using 51, 31, and 15 taps. . 29 5.2 Cascaded configuration of the implemented half-band FIR filter with 51, 31 and 15 taps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 Sinusoidal signal upsampled by a factor of 2 and filtered by a FIR filter. 30 xvii List of Figures 5.4 Block diagrams of a first-order ∆Σ modulator: (a) time-domain rep- resentation and (b) corresponding z-transform representation. . . . . 31 5.5 Block diagram of the z-transform of a second order ∆Σ modulator. . 32 6.1 Block diagram of the proposed system, with the DSP section high- lighted in green and the circuit section in peach. . . . . . . . . . . . . 34 6.2 Power spectrum of the ∆Σ modulated output showing the signal com- ponents and noise components, used for SNR analysis. . . . . . . . . 36 6.3 PSD of an ideal second order ∆Σ modulator driven by a non-quantized sinusoidal input with f0=4410 Hz, with output resolution ranging from 7 to 3 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4 PSD of a second order 7-bit ∆Σ modulator driven by both a non- quantized and a 16-bit quantized sinusoidal input. . . . . . . . . . . . 38 6.5 One period of the scaled ∆Σ modulated output compared with the BD PWM signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6 PSD of the BD PWM driven by both a non-quantized and a 16-bit quantized sinusoidal input with f0= 4410 Hz. . . . . . . . . . . . . . 39 6.7 THD and THD+N of the BD PWM signal driven by a non-quantized sinusoidal input with f0=1 kHz, for input amplitudes ranging from 0 to 6 dBFS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8 THD and THD+N of the BD PWM signal driven by a non-quantized sinusoidal input with f0=1 kHz, for input amplitude levels ranging from -120 to 0 dBFS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.9 THD and THD+N of the BD PWM signal for a 16-bit quantized sinusoidal input with f0=1 kHz, with input amplitude levels ranging from -120 to 0 dBFS. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.10 THD and THD+N of the BD PWM signal versus frequency from 20 to 9 kHz with a non-quantized sinusoidal input with -5 dBFS input amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11 THD and THD+N of the BD PWM signal versus frequency from 20 to 9 kHz with a 16-bit quantized sinusoidal input with -5 dBFS input amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.12 Implementation of Dead time on A- and B-Sides. Zoomed-in views il- lustrating the added dead time between the high-side (PMOS1/PMOS2) and low-side (NMOS1/NMOS2). . . . . . . . . . . . . . . . . . . . . . 43 6.13 Time-domain representation of the triangular noise and the inverted triangular noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.14 PSD of the BD PWM signal driven by triangular noise. . . . . . . . . 45 6.15 Output power stage of the Class D power amplifier implemented as an H-bridge circuit and simulated in LTspice. . . . . . . . . . . . . . 46 6.16 Frequency response of the RLC filter. . . . . . . . . . . . . . . . . . . 47 6.17 Schematic of the PCB layout designed in KiCad. . . . . . . . . . . . . 48 7.1 SNR and SINAD versus input signal level for a second-order 7-bit ∆Σ modulator, driven by a sinusoidal with and without 16-bit quantiza- tion for different input signal levels at f0 = 4410 Hz. . . . . . . . . . 50 xviii List of Figures 7.2 SNR and SINAD versus input signal level for the BD PWM output, driven by a sinusoidal input with and without 16 bit quantization at f0= 4410 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3 (a)BD PWM output voltage using different dead times. (b)Switching current at different dead times. . . . . . . . . . . . . . . . . . . . . . 52 7.4 SINAD versus dead time for a BD PWM driven by a 0 dBFS 16-bit quantized sinusoidal input at f0=4410 Hz. . . . . . . . . . . . . . . . 53 7.5 A 3D render of the PCB in KiCad. . . . . . . . . . . . . . . . . . . . 54 7.6 PSD of the power amplifier output at fundamental frequencies 882, 4410, 8820, and 17640 Hz with a sinusoidal input signal of -11 dBFS and an 11 ns dead time. . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.7 THD+N frequency sweep of the simulated power amplifier, driven by a sinusoidal with input signal level of -11 dBFS and 11 ns dead time. 56 7.8 Input signal level sweep showing the resulting SNR/SINAD of the simulated power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . 57 7.9 THD/THD+N versus RMS output voltage VRMS. . . . . . . . . . . . 58 7.10 Overview of the resistive and quiescent power losses in the audio power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.11 Apparent power efficiency versus RMS output voltage for the simu- lated power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 xix List of Tables 3.1 Different PWM modulation variants based on edge detection and out- put levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Non-ranked list of the top 7 microcontroller candidates . . . . . . . . 35 6.2 Comparison of the switching parameters of the MOSFETs on the PCB and in LTspice. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 List of circuit components and their values. . . . . . . . . . . . . . . . 46 6.4 List of selected circuit components and their values. . . . . . . . . . . 47 8.1 Performance Comparison of Technical Literature and Commercial Class D Audio Amplifiers for Bone Conduction Hearing Aids with Piezoelectric Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 xx 1 Introduction 1.1 Background The human ear is a complex organ that serves multiple functions and plays a key role in daily life. It helps facilitate communication and shapes the way we interact with the world. It consists of three different regions: the external ear, the middle ear, and the inner ear [2]. These three regions have different functions but work together to process sound and convert them into neural impulses. These impulses travel to the brain, where they are processed and interpreted as sound. When discussing the sense of hearing, it is divided into two distinct components: bone conduction (BC) and air conduction (AC). In AC hearing (ACH), sound waves enter the outer ear, travel through the middle ear, and cause the eardrum to vibrate [3]. The vibrations are further transmitted into the inner ear until they reach the cochlea, which in turn converts the vibrations into nerve signals. The second component, BC hearing (BCH), refers to the auditory response of vibrations through the human skull. These vibrations continue to travel through the skull until they reach the inner ear, where they stimulate the cochlea and result in the sensation of hearing. When an individual has a hearing threshold of 25 dB or higher, he or she is diagnosed with hearing loss, which can severely affect the quality of life of that individual [4, 5]. In general, there are three main types of hearing loss: sensorineural, conductive, and mixed hearing loss [6]. Sensorineural loss affects the inner ear or nerve signals, while conductive hearing loss affects the outer and middle ear. Mixed hearing loss is a mixture of the two. AC does not work as intended for a person with conduction hearing loss, which results in a higher hearing threshold for sound traveling through the air. Patients diagnosed with conductive or mixed hearing loss can achieve an improved hearing threshold using a bone conduction hearing aid (BCHA) that can be implanted or extrinsic [7, 8]. Implanted hearing aids can be percutaneous or transcutaneous. Percutaneous devices are surgically implanted devices directly at- tached to the temporal bone, with an abutment protruding through the skin [9]. In transcutaneous devices, the implanted part and the external processor of the hearing aid are connected by magnetic discs, hence no skin penetrating abutment is needed [10, 11]. 1 1. Introduction 1.2 Research Gap and Motivation Today, modern BCHAs use integrated circuits (IC), such as complementary metal oxide semiconductor (CMOS) technology, to power their speakers due to their low power consumption. The external component of the hearing aid, located outside the body, is powered by a battery. Reducing power consumption of the electronics is important to ensure a long battery life and thus improve the quality of life of users. Designing efficient power amplifiers in BCHAs with low power consumption is a complex task that demands a significant time, effort, and high development costs. Once developed, ICs offer several advantages, such as the capability for mass production at a low cost per unit, compact size, and energy efficiency. Although power amplifiers designed with discrete components might not reach the same level of performance as ICs, they offer a shorter integration timeline and are more cost- effective during the early design phases. If the power amplifier stage can be built using discrete power-MOSFETs while still delivering performance close to that of an integrated circuit, it will serve as an enabler for many products. To the best of the authors’ knowledge, no Class D amplifiers for piezoelectric ac- tuators designed with discrete components are found in either commercial products or technical literature. Even Class D amplifiers for piezoelectric actuators with in- tegrated solutions are scarce in technical literature, and only in the last couple of years some literature has been published on the topic. This gap highlights the need for further research into efficient, high-performance power amplifiers using discrete component solutions for bone conduction hearing aids. 1.3 Aim and Research Question The aim of this thesis is to develop a design and simulation framework of a digital Class D power amplifier for piezoelectric actuators in BCHAs, using off-the-shelf discrete components. The objective is to achieve performance levels close to those of ICs in modern BCHAs by achieving low total harmonic distortion (THD) and total harmonic distortion plus noise (THD+N), high apparent efficiency, and mini- mized power consumption. This approach seeks to provide a cost-effective and faster alternative to the traditional IC development process, filling a gap in the current market. Ultimately, improving the quality of life of users by prolonging battery life and improving audio performance. To achieve this aim, the thesis will address the following question: I. Is it feasible to design and implement a microcontroller-based digital Class D power amplifier using discrete components for piezoelectric actuators in BCHAs, and to achieve performance comparable to integrated solutions? 2 1. Introduction 1.4 Objectives The thesis aims to achieve the following objectives: I. Design and simulate a second order Delta Sigma (∆Σ) modulator that can be implemented for real-time audio processing on a microcontroller with audio input using the I2S (Inter-IC Sound) protocol II. Implement an efficient ∆Σ-to PWM conversion method for driving discrete power MOSFETs in the output stage of a Class D power amplifier III. Design a custom-made PCB for the proposed digital power amplifier system using off-the-shelf components IV. Optimize the second order ∆Σ modulator by experimenting with the bit depth in the quantized output, to maximize signal-to-noise ratio (SNR) and minimize noise V. Experiment with dead-time control to find an optimal dead-time that mini- mizes current spikes and prevents short circuits VI. Minimize THD and THD+N in the digital Class D audio amplifier using test signals within the 20 Hz to 20 kHz audio frequency range VII. Achieve a quiescent power consumption of < 1 mW VIII. Ensure apparent power amplifier efficiency of ≥ 80% IX. Provide recommendations for further development and potential improvements 1.5 Delimitations This section outlines the boundaries established for this thesis. • The audio input will be generated in simulation environment in MATLAB as an exclusively digital signal, with a sampling frequency of 44.1 kHz, and with 1000 samples represented in the form of a 16-bit quantized sinusoidal signal. The different frequencies chosen for the simulations are integer multiples of 44.1 Hz, ensuring that the waveform completes an integer number of cycles in order to avoid spectral leakage in the simulation environment. • Only off-the-shelf microcontrollers for driving the Class D amplifier will be investigated. • The modulation techniques will be limited to ∆Σ modulation and conversion to PWM for signal processing due to compatibility with digital systems and effective noise shaping characteristics. • The PCB will initially be designed using KiCad software and later printed, but not soldered as it is beyond the scope of this work. • Integrating the digital audio input from the sound card via I2s into the micro- controller and testing the H-bridge circuitry required expertise and time that exceeded the scope of this thesis. Therefore, they were designated for future work. • The piezoelectric actuator used as the output load will not be tested practically due to time constraints. Instead, its behavior will only be analyzed through simulations, where it will be modeled as a capacitor together with a series resistance. 3 2 Fundamentals of Audio Amplification in BCHAs This chapter begins with a brief overview of the key components in a typical dig- ital BCHA system, illustrated in Fig. 2.1 and highlights the specific components examined in this thesis. Next, the most widely used bone vibrators for BCHAs will be covered, including their key characteristics and operational principles. Then, the fundamental performance indicators of audio amplification will be introduced. 2.1 Overview of Digital BCHA Systems A generic block diagram of a digital BCHA is illustrated in Fig. 2.1. The hearing aid consists of a microphone, preamplifier, analog-to-digital converter (ADC), dig- ital signal processor, digital-to-analog converter (DAC), a power amplifier, and a receiver. For air conduction hearing aids (ACHAs), the receiver is in the form of a speaker, whereas for those operating on the principle of BC, the receiver is in the form of a transducer or actuator. In this work, the focus is only on the components within the orange sub-block in Fig. 2.1. Figure 2.1: A generic digital BCHA system. 4 2. Fundamentals of Audio Amplification in BCHAs 2.2 Vibration Technologies in BCHAs This section provides a brief overview of the most commonly used vibrators for BCHAs, focusing on electromagnetic transducers and piezoelectric ceramic actua- tors. 2.2.1 Electromagnetic Transducers Over the years the preferred transducer for hearing aids has been the electromag- netic (EM) transducer, due to its efficient mechanism and ability to generate high levels of sound pressure [12, 13]. Fig. 2.2 illustrates two widely used types of EM transducers: the B71 and the B81. The transducer consists of a voice coil, a mag- net, and an acoustic cavity. When an electrical current is applied to the coils, an electromagnetic field is generated, in turn generating static magnetic flux in the air gaps. This causes a displacement in the acoustic diaphragm, creating vibrations or sound [14]. However, there are known disadvantages with EM speakers, such as the need of a large form factor to generate a high sound pressure level (SPL). This is primarily due to their low impedance value, typically ranging from 4 to 32 Ω [12]. As a result, the amplifier must supply large electrical current through the voice coil to generate a high SPL. This high current demand leads to increased power consumption, which is a problem for battery powered devices. Thus, regardless how efficiently you design the amplifying circuit, the EM transducer inherently limits the battery life. (a) (b) Figure 2.2: (a) Cross-sectional view of the B71 BC transducer. (b) Cross-sectional view of the B81 or Balanced Electromagnetic Transducer (BEST). Both images from [14]. Allowed by author to use. 5 2. Fundamentals of Audio Amplification in BCHAs Figure 2.3: Structure of a generic piezo actuator 2.2.2 Piezoelectric Ceramic Actuators In recent years, the piezoelectric ceramic actuator has gained significant attention, due to its power efficiency, low weight, and its thin construction, allowing for more compact speaker designs [15]. The actuator consists of a piezoelectric ceramic element (piezoelement), which is mounted on an acoustic diaphragm or a film, and a housing that functions as an overall enclosure containing the speaker components. The generic structure of a piezoelectric speaker is illustrated in Fig. 2.3. Common construction materials are polycarbonate (PC) for the housing, plastic resin or metal for the film, and lead zirconate titanate (PZT) for the piezoelement [12]. When the piezoelement receives a voltage, the ceramic membrane deforms and begins to bend upward and downward depending on the voltage applied, which in turn causes the film to vibrate and generate sound waves [15, 16]. 2.3 Performance Measures of Audio Amplifiers 2.3.1 Dynamic Range The dynamic range is a very important indicator in audio systems, as it represents the range between the loudest signal and the quietest representable signal, highlight- ing the ability of the audio amplifier system to capture both very quiet and loud sounds. For a 16-bit digital system, the smallest representable value in the system is 1 least significant bit (1 LSB), and the maximum value 0 dBFS corresponds to all bits set to ’1’. The theoretical dynamic range for an N -bit audio signal is given by the formula: Dynamic Range (dB) = 6.02N, (N = number of bits) Thus, the theoretical dynamic range for a 16-bit system is 96.32 dB, which means that the maximum value is 96.32 dB above the quietest value. 6 2. Fundamentals of Audio Amplification in BCHAs 2.3.2 Signal-to-Noise Ratio The SNR is an indicator used to express the ratio between the signal and the noise produced by the amplifier. Sources of noise can include quantization error, thermal noise from the circuit components, and radio frequency interference, among others. If the impedance is constant for both the signal and the noise the SNR can be expressed as: SNR = 10logP0 Pn = 20 logV0 Vn (2.1) where P0 and V0 represent the power and output voltage of the fundamental fre- quency component of the audio signal, respectively. Pn and Vn denote the power and voltage output noise within the audio spectrum 20 to 20 000 Hz. When measuring the SNR, only the ratio of power of the fundamental and the power of the noise is considered, with the power of the harmonics being excluded. 2.3.3 Distortion Metrics The audio quality is of high importance in hearing aid systems. To reproduce real- world sound accurately, it is very important to minimize the distortion. Distortion in audio systems implies an alteration of the output signal from the original input [17], and it is typically generated by unintended artifacts introduced by components within the audio system. In hearing aids, there are two standard audio quality metrics, THD and THD+N. The formula for THD is given by [12]: THD = √√√√ K∑ i=1 V 2 i V 2 0 = √√√√ K∑ i=1 Pi P0 (2.2) where V0 is the RMS voltage of the fundamental frequency component, Vi is the RMS voltage of the harmonics. This expression can be reformulated in terms of power where, P0 is the power of the fundamental frequency, Pi is the power of the harmonics and K is the index of the harmonics up to 20 kHz [12]. In the field of audio quality, THD+N is the most commonly used and reliable indicator for audio quality due to the addition of both harmonic distortion and noise. The formula for THD+N is given by [12]: THD + N = √√√√ K∑ i=1 V 2 i V 2 0 + V 2 n V 2 0 = √√√√ K∑ i=1 Pi P0 + Pn P0 (2.3) where once again V0 and P0 are the RMS voltage and the power of the fundamental frequency respectively, while Vn is the RMS voltage of the noise within the bandwidth of interest, usually in the audio spectrum 20 to 20000 Hz. This expression can be written in terms of dB as: THD + NdB = 20 log10 √√√√ K∑ i=1 V 2 i V 2 0 + V 2 n V 2 0 = 10 log10 ( K∑ i=1 Pi P0 + Pn P0 ) (2.4) 7 2. Fundamentals of Audio Amplification in BCHAs In technical articles and literature another performance metric called signal to noise and distortion ratio (SINAD) is often presented, and is defined as [18]: SINADdB = 10log K∑ i=1 P0 Pn + Pi = 20log K∑ i=1 V0√ V 2 n + V 2 i (2.5) where P0 and V0 represent the power and voltage of the fundamental signal, re- spectively. Pn and Vn denote the power and voltage of the noise, while Pi and Vi represent the power and voltage of the signal harmonics. By rearranging the terms in THD + NdB it is evident that (2.4) and (2.5) are related by a negative sign: SINADdB = −THD + NdB The total harmonic distortion (THD) in commercial BCHAs is typically measured and reported according to established standards such as IEC60118. For BCHAs common test frequencies are 500, 800, 1600 and 3200 Hz for certain sound pressure levels (SPL) [19, 20]. Acceptable (THD) values vary depending on the type of hear- ing aid used, but a general guideline is that the distortion should not be greater than 10% for a given frequency [21]. For percutaneous BCHAs devices, such as the Cochlear Baha 6 the THD is less than 0.3%, and for transcutaneous BCHAs devices, such as the Oticon Sentio 1 Mini the THD is less than 1% for frequencies (800 to 3200 Hz). In comparison, for BCHAs with piezoelectric loads such as the Cochlear Osia 2, the THD is reported to be less than 5% above 600 Hz. 2.3.4 Efficiency of Switching Audio Amplifiers with Resis- tive Loads One of the key performance indicators in switching audio amplifiers with resistive loads is power efficiency, as it represents how much of the supplied energy is con- verted into audio output and how much of that energy is lost, typically as heat. When measuring power efficiency in a conventional amplifier with a resistive load, efficiency is determined by calculating the ratio of output power to input power (the supply) [16]. The input power Pin is expressed as the sum of the output power Po and the power lost Ploss: Pin = Po + Ploss (2.6) This is generally defined by using the average consumed power Pavg over one sinu- soidal signal period, given by the voltage v(t) and the current i(t) over one period T . Pavg = 1 T ∫ T 0 v(t) i(t) dt = VoIo cos(ϕ) (2.7) 8 2. Fundamentals of Audio Amplification in BCHAs The phase angle ϕ, appearing in the power factor term cos(ϕ) from (2.7), describes the phase relationship between the current (Io) and the voltage (Vo). Electromag- netic transducers are almost purely resistive, which implies that the current and the voltage are in phase, thus ϕ ≃ 0◦, and cos(0◦) = 1. From (2.6), the power efficiency η for resistive loads can be defined as: η = Po Pin = Po Po + Ploss (2.8) 2.3.4.1 Efficiency of Switching Audio Amplifiers with Piezoelectric loads Since piezoelectric actuators are capacitive in nature, they also consume reactive power, and their current leads their voltage by a phase shift ϕ of almost 90◦. This can be seen in Fig. 2.4, which visualizes the output voltage and current across the piezoelectric load in a switching audio amplifier. As a result, the term cos(ϕ) in (2.7) is approximately equal to cos(90◦) ≃ 0, making the average power delivered to the load appear significantly lower compared to that of a typical resistive load. Therefore, when (2.7) is used for determining the efficiency for piezoelectric loads, it will seem very low because the power in the circuit is flowing back and forth between the supply and the load. This makes it very difficult to put a meaningful measure on the amplifier’s efficiency, and therefore, (2.8) is rarely used as a performance metric in audio amplifiers driving piezoelectric loads. Figure 2.4: Output voltage and current over the piezoelectric actuator in a switch- ing audio amplifier, illustrating the 90◦ phase shift. 9 2. Fundamentals of Audio Amplification in BCHAs An alternative method for calculating efficiency with loads of capacitive nature is proposed in [12], based on apparent power, Papp. Apparent power, represented by the yellow arrow in the power triangle shown in Fig. 2.5, is measured in Volt- Amperes (VA) and represents the vector sum of active power, measured in watts (W), and reactive power, measured in Volt-Amperes reactive (VAr). Based on the relationships in the power triangle, the apparent power can be given by the following: Papp = √ P 2 + P 2 reac (2.9) where, P is the active power and Preac is the reactive power in the circuit. Apparent power is the total amount of power flowing in an AC circuit and represents the average power without taking the phase into account, expressed as: Po,app = Vo,RMS Io,RMS (2.10) here Po,app is the output apparent power and Vo,RMS and Io,RMS are the RMS output voltage and current over the piezoelectric load. For a load with impedance |ZL(ω)|, at the fundamental angular frequency ω, Io,RMS is given by: Io,RMS = Vo,RMS |ZL(ω)| (2.11) by inserting (2.11) into (2.10) yields: Po,app = V 2 o,RMS |ZL(ω)| (2.12) Figure 2.5: Power triangle, showing the relationship between active power, reactive power, and apparent power. 10 2. Fundamentals of Audio Amplification in BCHAs 2.3.4.2 Power losses in Switching Audio Amplifiers with Piezoelectric Loads Based on (2.8), the piezoelectric amplifier’s apparent power efficiency can be formu- lated as [12]: ηPZ = Po,app Pin = Po,app Po,app + Ploss (2.13) where Pin is the average input power consumed by the supply and Ploss is the total power loss in the amplifier for a piezoelectric load. Since the average active power P in (2.9) is around 0 for a piezoelectric load the apparent power will consist mainly of the reactive component Preac. The total power loss Ploss in (2.13) can be calculated as [12]: Ploss = PQ + PCL + PSW + PBD + PFILT (2.14) here the total power loss is the combination of quiescent power PQ, conductive power PCL, switching power PSW, body-diode power PBD, and piezo output filter power losses PFILT. The amplifier’s quiescent power losses PQ represents the power consumption when the amplifier is in an idle state, receiving only background noise, and is given by: PQ = VDD IQ (2.15) where VDD is the supply voltage and IQ is the quiescent current drawn from the supply. Conduction power loss, PCL, refers to the power dissipated during the brief time period when the MOSFET is conducting and acts like a resistor RDS(on). This can be calculated as: PCL = I2 o,RMS RDS(on) (2.16) in which I2 o,RMS is the RMS output current and RDS(on) is the on-state drain–source resistance during conduction. The switching power losses, PSW is a combination of two components, the charging and discharging of the parasitic capacitances in the MOSFET, and the transition loss during switching. The first component can be estimated by calculating the energy stored in each parasitic capacitor CP of the MOSFET: EC = 1 2CP V 2 CP (2.17) where VCP is the voltage over respective parasitic capacitance. Each parasitic ca- pacitance is charged and discharged every cycle with the switching frequency FSW. Thus, the average consumed power PC in each parasitic capacitance is given by: PC = FSW EC = FSW CP V 2 CP (2.18) 11 2. Fundamentals of Audio Amplification in BCHAs by summing over every parasitic capacitance in the MOSFET the following expres- sion is obtained: PC = ∑ i FSW CP,i V 2 CP (2.19) the second component, the transition power loss can be estimated by: Ptrans = VDD Îo 2 ttrans FSW (2.20) where VDD is the supply voltage connected to the MOSFET, Îo is the peak output current through the MOSFET and ttrans is the transition time. Since one period has two transitions ON-OFF and OFF-ON a factor of two is needed. By combining the two components (2.19) and (2.20) the complete switching loss formula is yielded [12]: PSW = ∑ i (FSW V 2 CP CP,i) + VDD Îo 2 ttrans FSW (2.21) the gate driver power loss Pg is given by [22]: Pg = Qg FSW VGS (2.22) here, Qg is the total gate charge and VGS is the gate to source voltage. Body-diode losses PBD occur at every switching instance due to the conduction, and reverse recovery charge of the MOSFET’s body-diode, located between source and drain. Body diode losses can be estimated by calculating two components: dead time power loss Pdt, and reverse recovery loss Prr of the body diode. The first component can be estimated by calculating the losses associated with the reverse- recovery charge of the body diode, given by: Prr = Irrm trr VSD FSW (2.23) where Irrm is the maximum body diode reverse-recovery current, trr is the body diode reverse recovery time, VSD is the body-diode source-to-drain voltage. The second component, Pdt is given by: Pdt = Îo tdt VSD FSW (2.24) once again Îo is the peak output current and tdt is the implemented dead-time. By combining equations (2.23) and (2.24) the complete body-diode loss formula yields [12]: PBD = VSD FSW (Îo tdt + Irrm trr) (2.25) The piezoelectric output filter power loss PFILT, arises from the current ripple in the output signal shown as the blue curve in Fig. 2.6 and the dielectric losses in the piezoelectric actuator at the audio frequency, where the energy is converted into heat in the material. If there had been zero losses in the output signal, the output 12 2. Fundamentals of Audio Amplification in BCHAs Figure 2.6: Output current trough the piezoelectric actuator together with the ideal audio current. current would look like the red audio signal in the plot. This loss can be expressed as: PFILT = I2 o,RMS |ZL(ω)| cos(ϕ) + CPZ V 2 o,RMS 2π Faudio DF (2.26) where |ZF(ω)| cos(ϕ) corresponds to the resistive losses of the real part of the output filter at the audio frequency Faudio, CPZ represents the capacitance of the piezoelec- tric actuator, and DF corresponds to the dissipation factor of the specific piezo- electric actuator. Since the output current consists of both the audio frequency component as well as the switching frequency component, it can be formulated as: Io,RMS = IAudio + IRipple. Thus, the resistive losses of PFILT will be treated in this work as a lower bound for the losses occurring at audio frequency. Theoretically, the resistive losses occur at both the audio frequency as well as on the switching frequency and its harmonics, but this is not included in this model. The power loss model developed in this work is based on the power loss model in (2.14). However, since the simulation model has limitations PSW, given in (2.21) will be replaced with Pg in (2.22). Additionally, due to limitations in accurately simulating the body-diode power losses PBD (2.25), these losses are excluded in the analysis in this work. This exclusion introduces an unavoidable potential source of error, the adjusted power loss Ploss,adj can be expressed as: Ploss,adj = PQ + PCL + Pg + PFILT (2.27) 13 3 The Digital Class D Audio Power Amplifier This chapter presents a detailed overview of the key components of a Class D audio power amplifier. It begins with a brief comparison of different amplifier classes and then gives an explanation regarding Class D amplifier operation, with an emphasis on the modulation stage. The chapter then details the characteristics of MOSFETs, covers information on various configurations of output stages, and discusses the output series resonance filter. 3.1 Overview of Audio Power Amplifier Classes The audio power amplifier is an essential component in most audio systems. It is usually situated in the final stage of an audio amplifier block, where it transforms a low-power signal into a high-power output signal capable of driving a load. Tradi- tional analog power amplifiers are classified into different classes depending on how they function. Some of these include Class A, B, AB, and others [23]. The class A amplifier is a commonly used amplifier topology that uses only one transistor in the output stage and has advantages such as high gain, low signal dis- tortion, and good linearity [24, 25]. One drawback with this amplifier is that the transistor conducts current throughout the entire waveform cycle. This implies that the transistor is always on, which generates excessive heat and a continuous loss of power as given by (2.7). As a result, the amplifier has low power efficiency, with the theoretical maximum power efficiency of class A amplifiers only around 50% for a resistive load. Class B amplifiers address some of the efficiency and heating problems associated with Class A designs and are essentially an improved version of the Class A ampli- fier. A generic Class B amplifier circuit uses a push-pull output configuration with two complementary transistors, where each transistor takes turns conducting each positive or negative cycle. Class B amplifiers can achieve higher power efficiency compared to Class A, with a maximum theoretical power efficiency of 78.5%, as given by (2.7). One major drawback associated with Class B amplifiers is that they suffer from linearity issues, where crossover distortion is the main limitation [25]. 14 3. The Digital Class D Audio Power Amplifier To eliminate the distortion issues associated with Class B amplifiers, the Class AB amplifier was developed [25]. It combines the topology characteristics of both Class A and Class B. The Class AB amplifier thus removes the crossover distortion of a Class B amplifier while offering higher efficiency than the Class A. The typical power efficiency for a Class AB amplifier falls in the range of 50% to 78.5%, as given by (2.7). Class D amplifiers, which utilize high-speed switching transistors, were first intro- duced in the late 1950s, and are now regarded as one of the most promising technolo- gies for audio power applications [17, 23]. They have a theoretical power efficiency of 100%, but in reality, it is between 90% and 95% for a resistive load, as calculated using (2.7) [26]. The development of these amplifiers has been driven by the need to fit more power capability into a smaller space while at the same time dissipating less heat. Something that is very attractive in various modern audio applications such as mobile phones and hearing aids. They have many advantages over previously named power amplifiers; these include small size, low heat dissipation, low power consumption, and high efficiency. One major drawback of Class D amplifiers has historically been the distortion associated with their switching operation, but with advancements in technology, this issue has become significantly less problematic. A Class D amplifier can be configured as either a half or full bridge amplifier, both with their own advantages and disadvantages. The full bridge stage includes twice as many switching devices compared to the half bridge, resulting in higher costs and higher switching losses. However, the full bridge only requires half the power supply voltage to realize the same output voltage capability. Additionally, no current flows through the load when both sides are either off or on simultaneously, which can be utilized when optimizing switching. The full-bridge is also referred to as an H-bridge because the circuit has the shape of the letter H. An illustration of a H-bridge is shown in Fig. 3.1. PMOSA VrailA NMOSA RGate N1Gatesignal RGate P1Gatesignal LPfilter Speaker LPfilter VrailB RGate N2Gatesignal RGate P2Gatesignal NMOSB PMOSB Figure 3.1: Schematic of an H-bridge Class D amplifier with high-side PMOS and low-side NMOS, driving a speaker through a low-pass filter. 15 3. The Digital Class D Audio Power Amplifier In the H-bridge schematic shown in Fig. 3.1, N-channel MOSFETs are situated on the low-side, while P-channel MOSFETs are on the high-side. The gain of the Class D amplifier is equal to the ratio of the rail voltage VRail, and the input peak voltage V̂i: Gain = VRail V̂i . (3.1) 3.2 Modulation Stage The Class D amplifier modulator transforms the input audio signal into a high- frequency switching signal [27]. This signal is used to drive the switching stage on and off, thus amplifying the signal and delivering it to a load, either a loudspeaker or a transducer. The most widely used modulation techniques include pulse width modulation (PWM), Delta-Sigma (∆Σ) modulation, and self-oscillating control [23]. In this project, ∆Σ modulation will be utilized in combination with digital PWM. 3.2.1 PWM Signal Generation PWM can be generated in both the digital and analog domains. In the analog do- main, an audio frequency signal with a frequency typically ranging from 20 Hz to 20 kHz is compared to a high frequency carrier in the form of a sawtooth or triangular waveform with a frequency typically ranging from 0.1 to 1 MHz, using a comparator [27]. The output of the comparator is a high-frequency switching waveform in which the amplitude of the input signal is represented in the pulse width. This allows the input to control the duty cycle of the square wave, that is, the proportion of time the wave is in the high or low state. PWM is generally classified into two different variants, where the first is based on the edge characteristics of the carrier wave which can either be single-sided or double-sided. The second variant is determined by the number of output levels in the PWM signal, two (AD) or three (BD) [28]. A single-sided PWM signal employs a sawtooth carrier wave, whereas a double sided PWM signal uses a triangular car- rier wave. These classifications are summarized in Table 3.1 [28]. Edge Detected Output Levels Single-Sided Two (AD) Single-Sided Three (BD) Double-Sided Two (AD) Double-Sided Three (BD) Table 3.1: Different PWM modulation variants based on edge detection and output levels. 16 3. The Digital Class D Audio Power Amplifier Single-sided BD PWM, as highlighted in blue in Table 3.1 was used for the modu- lation stage in this thesis, due to the simplicity of integrating it into a simulation environment. The generation of the single-sided BD PWM is implemented in a DSP system with an internal timer, which counts up to a fixed value within one cycle. During each cycle the value of the timer is compared to the value of the input sig- nals which ultimately defines the duty cycle of the generated PWM signal. For a single-sided BD PWM, the system has two input and output signals, with one being an inverted version of the other, representing the PWM fed to the A and B sides of the H-bridge. For simplicity, the input signals are usually simulated as sinusoidal waveforms. The resulting single-sided BD PWM signal is the difference between the PWM signals at A and B-side. In the H-bridge schematic shown in Fig. 3.1 the A side corresponds to the left side, while the B side corresponds to the right side. The PWM signal at A-side is illustrated in Fig. 3.2a and generated from the original input, and the PWM signal at B-side, illustrated in Fig. 3.2b is generated by the inverted input. The resulting signal is illustrated in Fig. 3.2c. The B-side should always receive an inverted version of the signal fed to A-side, regardless of the input signal. 17 3. The Digital Class D Audio Power Amplifier (a) A-side of the BD modulated PWM. (b) B-side of the BD modulated PWM. (c) The resulting BD modulated PWM. Figure 3.2: (a) A-side and, (b) B-side PWM signal, and (c) the resulting BD modulated output. 18 3. The Digital Class D Audio Power Amplifier 3.3 Class D Power Amplifier Stage The proposed power stage of the amplifier consists of two circuits: the amplifica- tion stage and a series-resonant RLC circuit, which together amplify the signal and remove unwanted frequency components. The power stage in Class D amplifiers comprises power MOSFETs due to their high switching speed and the ability to easily achieve a rail-to-rail output using a relatively low input current [17]. In switching applications where MOSFETs are utilized, the aim is to rapidly tran- sition between the on and off states of the transistor [29]. When the MOSFET is in the on state, it has low resistance, thus enabling maximum current flow with low impedance. In contrast, during the off state, the MOSFET presents high resis- tance, effectively stopping current flow. In high-frequency applications, the parasitic characteristics of the MOSFET are very important as they limit the switching speed. The total gate charge value of a MOSFET Qg is the amount of charge applied at the gate capacitance Cg required for the MOSFET to switch on [30]. Measured in Coulombs (C), this value typically falls within the nano Coulomb nC range. In high-frequency applications, minimizing the gate charge is of high importance to enhance efficiency. The amount of gate current Ig required from the drive circuit to switch the MOSFET in a desired time can easily be calculated with the following formulas, where VGS once again denotes the gate to source voltage and tSW is the switching time of the MOSFET: Qg = Cg VGS and Ig = Cg dVGS dtSW (3.2) where Qg = tSW Ig (3.3) For example, a MOSFET with a gate charge of Qg = 10 nC can be switched on in 10 µs if a gate current of 1 mA, is applied to the gate or in 10 ns if the gate current is raised to 1 A. The role of the gate driver circuit is to amplify the output signal, thus enhancing the switching speed of the output stage. 3.3.1 Dead Time Control MOSFETs operate like switches that, when turned on at the right moment, can am- plify the input signal at the gate. There are several configurations that can be used to switch the MOSFETs depending on specific application. Fig. 3.3 illustrates the positive and negative transition modes, which lead to either a positive or a negative output. The positive transition mode is illustrated in Fig. 3.3a and the negative transition mode in Fig. 3.3b. Furthermore, Fig. 3.4 presents the zero transition modes for an H-bridge configu- ration, all of which result in zero output. Fig. 3.4a shows the first zero transition 19 3. The Digital Class D Audio Power Amplifier (a) (b) Figure 3.3: (a)First transition mode of the switches producing a positive output, and (b) second transition mode which gives a negative output. mode where both high-side MOSFETs are open, Fig. 3.4b shows the second zero transition mode where both of the low-side MOSFETs are open and Fig. 3.4c illus- trates the third zero transition mode where all MOSFETs are open. When a PWM gate signal is applied to an H-bridge circuit utilizing MOSFETs, there can be a brief moment when both the high-side and low-side MOSFETs are turned on simultaneously or when one MOSFET turns on before the other has fully switched off. This can lead to a short circuit between the supply and ground and a large shoot-through current. Fig. 3.5 depicts the two possible short circuit scenarios, Fig. 3.5a illustrates a short circuit on the left side, and Fig. 3.5b illustrates a short circuit on the right side. To avoid this, dead-time control must be implemented in H- bridge circuits. Dead time is a transition period during which none of the MOSFETs on the same side of the H-bridge conduct at the same time. It can be controlled using analog circuitry or digitally with a microcontroller. Dead time also introduces significant distortion and must therefore be minimized while safely avoiding shoot- through [31, 17]. The dead time introduces a diode voltage drop as well as a voltage (a) (b) (c) Figure 3.4: Different switching modes that generate no output, therefore zero- modes. 20 3. The Digital Class D Audio Power Amplifier (a) (b) Figure 3.5: Unwanted switching modes that cause short circuits, which dead time control is designed to prevent. increase in the circuit, proportional to the dead time. A rule of thumb is to have a dead time longer than the switching time of the slowest MOSFET. 3.3.2 Series-Resonant Circuits Fig. 3.6 shows an illustration of a series resonance circuit. The inductive reactance of an inductor XL rises linearly with the frequency, meaning it is proportional to the frequency (XL ∝ f) and is illustrated as the red straight linear arrow in Fig. 3.7. The value of the reactance XL is given by: XL = 2πfL = ωL In contrast to the inductor, the capacitive reactance of a capacitor XC is inversely proportional to the frequency (XC ∝ f−1) and is illustrated as the blue hyperbolic curve in Fig 3.7. The value of the reactance XC is given by: XC = 1 2πfC = 1 ωC Figure 3.6: Series resonance circuit showing an RLC circuit consisting of an AC voltage source, a resistor, an inductor, and capacitor [32]. 21 3. The Digital Class D Audio Power Amplifier Figure 3.7: Impedance versus frequency for capacitance and inductance, and high- lighting the resonance frequency. By setting XL = XC, we have: 2πfL = 1 2πfC Rearranging terms: f 2 = 1 (2πL)(2πC) = 1 4π2LC Taking the square root: f = √ 1 4π2LC Thus, the resonant frequency is given by: fr = 1 2π √ LC (Hz) (3.4) Alternatively, the angular resonant frequency is: ωr = 1√ LC (rads) Another important metric is the Quality or Q factor of the circuit, which essentially determines the sharpness of the resonance peak. The resistance value determines the width of the curve; a lower resistance results in a sharper and narrower curve. The Q-factor is given by [33]: Q = 1 ωrRC (3.5) 22 4 Digital-to-Analog Converters This chapter provides a theoretical introduction to digital-to-analog converters (DAC). The discussion begins with an overview of conventional Nyquist rate converters, fol- lowed by an introduction to oversampling converters and ∆Σ converters. The chap- ter will specifically highlight differences in the quantization noise processes for each type of converter and demonstrate why ∆Σ DACs are often preferred in converter systems utilizing oversampling. 4.1 Decibels Relative to Full Scale The unit decibel relative to full scale, or dBFS, is essential in digital audio systems. It represents the input signal amplitude relative to the maximum achievable signal amplitude of a system before a phenomenon called clipping occurs. Clipping occurs when the system receives an audio input signal with an amplitude that exceeds the system’s maximum representable level. In digital audio systems, 0 dBFS represents the highest possible level without distortion. Due to the high risk of clipping, real- world playback audio systems almost always operate at input amplitude levels below 0 dBFS. More common signal amplitude values fall within the range of -1 to -20 dBFS to minimize distortion. The unit dBFS is also used to quantify the dynamic range of a digital audio signal. 4.2 Nyquist-Rate Digital-to-Analog Converters Digital to analog conversion (DAC) is a process that translates a discrete time digital input to a continuous time analog output signal [34]. An N -bit Nyquist-rate DAC operates at a sampling rate at or above the Nyquist criterion, fs ≥ 2fb where fs is the sampling rate and fb is the bandwidth of the sampled signal. Each sample is processed individually, and the converter lacks memory [35]. 4.2.1 Quantization in a Nyquist DAC The DAC’s performance is highly dependent on the accuracy of its circuit compo- nents. In addition, when the application demands higher resolution and linearity, the converter suffers from its slow operating speed. For the DAC to accurately represent the input, the number of quantization levels as defined by 2N should be maximized. The quantization step size represents the distance between two consec- 23 4. Digital-to-Analog Converters utive quantization levels and is defined as: q = Vmax − Vmin 2N − 1 (4.1) where Vmax and Vmin are the maximum and minimum values of the input signal. Since digital signals are discrete, the conversion process always introduces quanti- zation error, which is the difference between the quantized output and the input, defined by eq = Q(x) − x, where Q(x) is the quantized output and x is the input. The quantization error is always constrained by the range − q 2 ≤ eq ≤ q 2 , as can be seen in the probability density function (PDF) of the quantization error in Fig 4.1a. The quantization operation is a nonlinear process, because of the mapping of con- tinuous values to discrete levels [36, 35]. Due to this reason, three simplifying assumptions regarding the quantization error properties are generally made. 1. The error sequence, eq is assumed to be a random process with stationary properties. 2. The error sequence, eq is assumed to be independent across time and indepen- dent with the input sequence x. 3. The probability density function (PDF) of the quantization error sequence eq, is assumed to be uniform over the range −q/2 ≤ eq ≤ q/2. Assumption 3 gives the following [36]: p(eq) =  1 q , |eq| ≤ q 2 0, |eq| > q 2 (4.2) which can be visualized in Fig. 4.1a. The following assumptions allow for the error to be visualized as white noise, thus the power spectral density (PSD) of the error will have uniform distribution within the Nyquist band as shown in 4.1b. (a) PDF of the quantization error in an ideal Nyquist-rate DAC. (b) PSD of the quantization error in an ideal Nyquist-rate DAC. Figure 4.1: PDF and PSD of the quantization error in an ideal Nyquist-rate DAC. 24 4. Digital-to-Analog Converters With these assumptions, the formula for the average quantization noise can be expressed as: ēq = E{eq} = ∫ ∞ −∞ eq p(eq) deq = 1 q ∫ q 2 − q 2 eq deq = 0 and the power of the quantization noise is represented by: σ2 e = E{(eq − ēq)2} = ∫ ∞ −∞ e2 q p(eq) deq = 1 q ∫ q 2 − q 2 e2 q deq = q2 12 (4.3) by substituting (4.1) into (4.3), under the assumption that Vmax = 1 and Vmin = −1 the following expression for quantization noise power is obtained σ2 e = q2 12 = 1 3(2N − 1)2 ≃ 1 3(22N) (4.4) 4.2.2 Signal-to-Noise Ratio in a Nyquist DAC To determine the SNR for a Nyquist DAC-generated PCM signal, the signal power must first be calculated. The input signal being quantized is assumed to be sinu- soidal signal with amplitude A, expressed as: x(t) = Acos(2πt T ). The quantization error ex is defined as the difference between the input signal x(t) and its quantized version x̂(t). ex = x̂(t) − x(t) (4.5) The average power of the signal is given by [36]: σ2 x = A2 2 (4.6) By substituting the resulting terms for average noise power in (4.4) and the average signal power in (4.6) into the formula for SNR provided in (2.1), the following expression is obtained [36]: SNR(dB) = 20log10 σx σe = 10log10 3 × 22N 2 ≃ 20 log10 A + 6.02 N + 1.76 This expression shows that the signal-to-noise ratio improves by around 6 dB for every increment in the number of bits in the quantizer. An audio signal quantized with 16-bits resolution has a theoretical maximum SNR of 98.08 dB. 25 4. Digital-to-Analog Converters 4.3 Oversampling Converters One way to ease the accuracy demand of analog devices is by using oversampling converters. An oversampling converter operates at a sample rate higher than the Nyquist criterion according to OSR = fs 2fB , where OSR abbreviates the oversampling ratio [35]. The OSR value is generally set to a multiple of 2, where the most common values are between 8 and 512. Oversampling converters that incorporate a loop filter with a feedback structure, such as the ∆Σ modulator, rely on preceding input values to generate the output, unlike Nyquist-rate converters, which process each sample individually. An oversampling converter requires more advanced digital circuitry and is slower than the Nyquist-rate converter, but it increases the accuracy and linearity. 4.3.1 ∆Σ Digital-to-Analog Converter A common type of oversampling converter is the Delta Sigma (∆Σ) DAC. In com- parison to other oversampling converters, it includes a loop filter, which subtracts the difference between the quantized output and the input signal, a process known as noise shaping. Noise shaping shifts the noise within the band of interest to higher frequencies outside of the band of interest; this concept will be further described in chapter 5. ∆Σ- modulation is mainly used to convert signals from a low-rate, and large-word-length format to a high-rate and low-word-length format [35]. For example, a signal input of 16 bit and a fs of 44.1 kHz, could be upsampled by 4, to a fs of 176.4 kHz, and a 1 bit word length. The DAC can be fully implemented in the digital domain, and the modulation order and the OSR of the converter determine the performance. A general first order ∆Σ DAC is composed of two main blocks, the interpolation stage where the upsampling and filtering occur and the ∆Σ modu- lator, shown in Fig. 4.2. As its name suggests, the modulator consists of a negative feedback loop ∆, an accumulator stage called Σ and an N-bit quantizer. 26 4. Digital-to-Analog Converters Figure 4.2: General block schematic of a first order ∆Σ DAC. A comparison of the different shapes of quantization noise, for Nyquist-sampled, oversampled and noise-shaped signals is illustrated in Fig. 4.3, showing how noise- shaping shifts the noise within the band of interest to higher frequencies outside of the band of interest. The figure highlights the desirable attributes regarding noise shaping. Figure 4.3: Comparison of the PSD of quantization noise for Nyquist sampling, oversampling, and noise-shaped signals. 27 5 Digital ∆Σ Modulation In this section, the fundamental theory regarding digital ∆Σ modulation is pre- sented. It begins with an introduction to the interpolation stage shown in Fig. 4.2, covering the principles and role of upsampling and filtering. Following this, the ∆Σ modulation loop shown in Fig. 4.2 is outlined, together with key principles such as noise shaping, and an overview of ∆Σ converter performance metrics. 5.1 Interpolation Interpolation has the role of increasing the sampling rate of a digital input signal while removing or attenuating spectral replicas created during upsampling [35]. In- terpolation is thus the combined function of upsampling and low pass filtering of an input signal. 5.1.1 Upsampling Upsampling is the process of increasing the sample rate of a signal by creating additional data points from an existing set of data points [35]. A common method is zero stuffing, which is performed by inserting OSR-1 zeros between each sample. This increases the sampling frequency fs to fs × OSR. When a signal undergoes upsampling, it introduces spectral replicas at fs, 2fs, ..., (OSR−1)fs where fN is the Nyquist frequency. To remove unwanted spectral replicas, a digital low-pass filter must be applied to the upsampled signal. 5.1.2 Digital Filters A digital filter is a system that performs a mathematical operation on a discrete time sampled input to modify the input signal [34, 37]. The general transfer function for a digital filter is: H(z) = b0 + b1z −1 + ...bnz−n 1 + a1z−1 + ...anz−n = Y (z) X(z) where X(z) represents the z-transform of the input signal and Y(z) represents the z-transform of the output signal. Taking the inverse z-transform yields the difference equation yn = −a1yn−1 − a2yn−2 − ... + b0xn + b1xn−1 + b2xn−2 + ... (5.1) 28 5. Digital ∆Σ Modulation which is the difference equation of the filter, and where an and bn are the filter coefficients [34]. The filter coefficients can be calculated to shape and filter the input signal in a certain way. The most common digital filters are infinite impulse response (IIR) filters and finite impulse response (FIR) filters [37]. IIR filters rely both on input and earlier output samples, as described in (5.1). They are usually of low order and requires less filter coefficients than FIR filters, which makes them faster. But IIR filters are not always stable and the phase shift is not linear. In comparison, FIR filters do not rely on prior output samples and can be described by putting all the ai coefficients to zero in (5.1). This filter is slower but has inherent stability and a linear phase. Due to this fact, FIR filters are more suitable for audio applications, as the phase information is more important than the speed [38]. 5.1.3 Half-Band FIR Filter A filter suitable for interpolation by a factor 2 are half-band filters [39]. The fre- quency response of a half-band filter should satisfy H(ej(2π f fs ) + H(ej2π(0.5+ f fs )) = 1, which causes nearly half of the impulse response samples to be zero, and therefore no computation is required for half of the taps in the filter. The ideal half-band FIR filter response is visualized in Fig. 5.1 represented by the black curve, with the light blue ideal magnitude scale on the left y-axis. The blue, red, and green curves correspond to filters with 51, 15, and 11 taps, respectively with the orange magnitude scale on the right y-axis. The cascaded configuration of these filters is visualized in Fig. 5.2. Figure 5.1: Frequency response of an ideal half-band FIR filter compared with compared with practical implementations using 51, 31, and 15 taps. 29 5. Digital ∆Σ Modulation Figure 5.2: Cascaded configuration of the implemented half-band FIR filter with 51, 31 and 15 taps. Fig. 5.3 depicts a signal upsampled by 2, stuffing 2-1 zeros in between every sample and creating a spectral replica at 9000 Hz. As can be seen above, by putting this through a half-band FIR filter, the signal is averaged and the spectral replica is removed. The original signal has a frequency of 1000 Hz, and a fs of 10 kHz. After upsampling, the sampling frequency is Fs = 20 kHz. To achieve a high oversampling ratio using only half-band filters, multistage interpo- lation must be employed [39]. In other words, cascaded upsampling by two combined with complementary filtering stages. For every interpolation stage, the demand on the transition band can be relaxed. Figure 5.3: Sinusoidal signal upsampled by a factor of 2 and filtered by a FIR filter. 30 5. Digital ∆Σ Modulation 5.2 First Order ∆Σ Modulator Feedback Loop As discussed in section 4.3.1, the first-order ∆Σ modulator feedback loop generally consists of three components: a feedback difference operation ∆, an accumulator Σ and an N-bit quantizer. Fig. 5.4 illustrates two block diagrams of a first-order ∆Σ modulator, Fig 5.4a presents the time-domain representation, and Fig. 5.4b depicts the corresponding z-transform block. The N-bit quantizer in the ∆Σ modulation loop introduces a quantization error de- scribed by e = u−y, where u is the input to the quantizer and y is the output. This quantization error is assumed to be uniformly distributed, making the model linear and easy to analyze in the Z-domain [35]. The output of the Z-block system in Fig. 5.4b can be described using the signal transfer function (STF), and the noise transfer function (NTF) as: Y (z) = STF (z)X(z) + NTF (z)E(z), (5.2) where Y (z) is the output, X(z) is the input and E(z) is the quantization error of the system. (a) Time-domain block diagram of a first-order ∆Σ modulator with an N-bit quantizer. (b) Z-transform block diagram of a first-order ∆Σ modulator with an N-bit quantizer. Figure 5.4: Block diagrams of a first-order ∆Σ modulator: (a) time-domain rep- resentation and (b) corresponding z-transform representation. 31 5. Digital ∆Σ Modulation Since the accumulator in the Z-block diagram in the system in Fig. 5.4b has the transfer function: H(z) = z−1 1 − z−1 , (5.3) the STF can thus be written as: STF (z) = Y (z) X(z) = H(z) 1 + H(z) = z−1, (5.4) which is essentially just a unit delay. And the NTF can be written: NTF (z) = Y (z) E(z) = 1 1 + H(z) = 1 − z−1, (5.5) which shows that the NTF is essentially a first order high pass transfer function, and is the part that contributes to the noise shaping in the ∆Σ modulator. 5.3 Higher Order ∆Σ Modulator Feedback Loops A ∆Σ modulation loop can be of different order and employ different feedback struc- tures. The number of integrators and feedback paths present in the modulation loop determines the order. Fig. 5.5 shows the Z-transform block of the second-order ∆Σ modulator. The second-order modulator’s transfer function in the Z-domain is given by: Y (z) = X(z)z−1 + E(z)(1 − z−1)2 (5.6) from this expression, the NTF can be formulated as [36]: NTF (f) = (1 − e−j2π f fs )2, (5.7) and furthermore the in-band noise power can be expressed as: σ2 n = σ2 eπ4 5 × OSR5 (5.8) Figure 5.5: Block diagram of the z-transform of a second order ∆Σ modulator. 32 5. Digital ∆Σ Modulation ∆Σ modulators of first and second order are inherently stable and no filter is thus needed in the feedback loop. For higher order modulators there are known stability issues, so the filters need to be designed carefully. The maximum SNR for a second order ∆Σ modulator can be approximated by [36]: SNR(dB) ≈ 20log10A+6.02N +1.76+10log10(5)−9.94×2+3.01(2×2+1)r, (5.9) where N is the number of bits in the quantizer, and r denotes the exponent of the OSR, defined as: r = log2(OSR). (5.10) For example, an OSR of 8 corresponds to 23, so r = 3 and OSR = 2r. 33 6 Method This chapter explains the methodology used in this project and gives a description of the design and simulation of each part. It starts with a block diagram of the proposed Class D power amplifier system, shown in Fig. 6.1. The entire system is developed within a simulation environment, with the intention of reflecting the practical system. To replicate a real-world scenario as closely as possible, and align with the configurations of a 16-bit 44.1 kHz digital audio sound card using the Inte- grated Inter-IC Sound Bus (I2S) format, the simulated input signal is designed with the same bit depth and sampling frequency. The input signal then goes into the DSP stage, where it goes through a series of upsampling and half-band filtering, thus increasing the sampling frequency fs with OSR = 8 to Fs = fs × 8, to align the ∆Σ modulated output frequency with the BD PWM switching frequency Fs = 352.8 kHz. After the interpolation stage the signal with sampling frequency Fs enters the ∆Σ modulator which reduces the resolution of the signal down to 7-bits. The output of the ∆Σ modulator is then converted into a BD PWM signal with dead-time control that is fed into the H-bridge power stage in LTspice software, which drives the piezoelectric actuator load. Figure 6.1: Block diagram of the proposed system, with the DSP section high- lighted in green and the circuit section in peach. 34 6. Method 6.1 Selection of Microcontroller An extensive literature review was conducted in order to select a suitable micro- controller (MCU) for this work. The objective was to find a microcontroller that met specific criteria: a high core frequency to facilitate dead-time control, a core type M33, M0+, or M4 with 32-bit operation, Phase-Locked Loop (PLL), and the availability of a development kit (Devkit). A development kit is required as it makes it easier to use the microcontroller and all its functions. A PLL can be used to con- trol the frequency in the microcontroller, between the input output and the internal clock. An ARM processor was required since it would make it easier to integrate with Cochlear’s products. Table 6.1 presents a non ranked list of the top seven identified candidates through this process, where the two chosen candidates MAX32650 and LPCXpresso55S69 are lined in blue, respective green. The LPCXpresso55S69 was the main micrcontroller for this work and was used together with its development kit, the LPCXpresso55S69-EVK. 6.2 Design and Simulation in MATLAB Initially, simulations of the second order ∆Σ modulator and the BD PWM will be on the ideal non-quantized ∆Σ modulation version with a floating-point sinusoidal input, to evaluate its performance. Later, a 16-bit quantized sinusoidal input will be introduced to reflect real-world scenarios. 6.2.1 Interpolation Interpolation was implemented using built-in upsampling functions to increase the sample rate, along with a custom made half-band FIR filter. The built-in “filtfilt” function was used to filter with a zero-phase delay. The half-band FIR filter was used due to its simplicity and efficiency when dealing with signals that use zero- stuffing and that are upsampled by a factor of 2. A second order ∆Σ modulator was implemented in MATLAB using an accumulator-based structure as proposed by [35]. The second order modulator was chosen for its simplicity in implementation and its inherent stability as its poles lie within the unit circle [40]. Table 6.1: Non-ranked list of the top 7 microcontroller candidates Model Core Interfaces PLL Devkit Apollo3 Blue Datasheet M33, 150 MHz I2C or I2S No Yes LPC55S6x M33, 150MHz SPI, I2C, or I2S Yes Yes Renesas RE01 M0+, 64 MHz I2C or simple SPI No Yes MAX32680 M4, 120 MHz Two I2C and I2S Yes Yes MAX32666 M4, 96 MHz I2C, QSPI or I2S Yes Yes EFR32BG22 M33, 76.8 MHz I2S or SPI Yes Yes MAX32650–MAX32652 M4, 120 MHz SPI, I2C or I2S No Yes 35 6. Method To reduce spectral leakage, the fundamental frequency f0 of the input signal sampled at fs = 44.1 kHz, is generated using the following formula: f0 = fs Q where Q is an integer determined by the equation: nsamples = P × Q where P is the number of periods. For example, by using a Q value of 10 and a P value of 1000, a signal with the fundamental frequency f0 = 4410 Hz is gener- ated. The signal is then interpolated to an OSR of 8, corresponding to a sampling frequency Fs of 352.8 kHz. 6.2.2 Design and Implementation of the ∆Σ modulator An important metric for the modulators performance is the SNR and SINAD, the evaluation of which is done in the frequency domain [41]. By summing the frequency bins in the band of interest and comparing them with the overall frequency band, the SINAD can be calculated according to (2.5). When calculating the SNR, the power of the harmonics was also excluded, according to (2.1). This analysis was performed on the output of the ∆Σ modulator as well as for the BD PWM signal. Fig. 6.2 depicts the half-sided power spectrum, where the blue curve represents the power spectrum, the yellow lines are the noise bins and the red lines are the signal bins of the fundamental tone. The noise bins and the signal bins are summed independently of each other and compared, to determine the SNR. Figure 6.2: Power spectrum of the ∆Σ modulated output showing the signal components and noise components, used for SNR analysis. 36 6. Method Frequency analysis experiments were initially conducted with different quantizer bit resolutions of the second order ∆Σ modulator to evaluate its performance. The PSD of the ideal second order ∆Σ modulator with a non-quantized input, and with output bit resolutions ranging from 7 to 3 bits, is shown in Fig. 6.3. It clearly demonstrates that as the number of bits decreases, the noise floor shifts upward reflecting the increase of quantization noise. Based on this observation, together with the aim of maximizing the performance a 7-bit quantizer in the ∆Σ modulator was chosen. In Fig. 6.4 the PSD of the second order 7-bit ∆Σ modulator with and without 16-bit quantized input is shown. The blue curve represents the PSD of the ideal ∆Σ modulator, while the orange curve corresponds to the PSD of the ∆Σ modulator with 16-bit quantized input. The noise floor is slightly lower and the power of the harmonic components are slightly reduced in the ideal ∆Σ modulator. Figure 6.3: PSD of an ideal second order ∆Σ modulator driven by a non-quantized sinusoidal input with f0=4410 Hz, with output resolution ranging from 7 to 3 bits. 37 6. Method Figure 6.4: PSD of a second order 7-bit ∆Σ modulator driven by both a non- quantized and a 16-bit quantized sinusoidal input. 6.2.3 Conversion of ∆Σ to BD PWM To convert the ∆Σ modulated signal into BD PWM, the principles of Single-Sided BD modulation, as explained in Section 3.2.1, were employed. Initially, this was implemented without dead-time control, working with a counter of 256 values, with the intention to mimic the counter function in the microcontroller. This results in a required clock frequency, denoted by fPWM. The required clock frequency control- ling the BD PWM is given by fPWM = 256 × Fs = 256 × 352.8 kHz = 90.3168 MHz. Since the counter has a value of 256, the output signals of the ∆Σ modulator lies in the interval [-128 to 127]. The output signals of the ∆Σ modulator were then scaled to the range [0 to 256], where a value of 0 indicates that the BD PWM signal re- mains low for the entire period, and 256 indicates it stays high for the entire period. For each output signal sample, the duty cycle value determines the proportion of the BD PWM period that the signal stayed high or low. The BD modulated PWM signal together with the ∆Σ modulated output is shown in Fig. 6.5. In this plot the ∆Σ modulated output is scaled to match the amplitude of the BD PWM. It is evident that the duty cycle of the pulse widths in the BD PWM signal accurately represents the amplitude values of the ∆Σ modulated output signal. Fig. 6.6 presents the PSD of the BD modulated PWM signal driven by both the ideal version with a non-quantized and a 16 bit quantized sinusoidal input. The curve in blue represents the PSD of the BD PWM with a 16 bit quantized input and the orange curve represents the PSD of the ideal version. The harmonics of the fundamental sinusoidal f0 can be observed at regular intervals n = 1, 2, 3.... × f0. In the greater frequencies, the PWM switching harmonics frequencies are also easily distinguished, with harmonics appearing at n = 1, 2, 3.... × fPWM, with upper and lower sidebands at fPWM ± n × f0. 38 6. Method Figure 6.5: One period of the scaled ∆Σ modulated output compared with the BD PWM signal. 6.2.4 Performance Analysis of BD PWM Other key performance metrics evaluated were the THD and THD+N values of the BD PWM signal, calculated using (2.2) and (2.3), respectively. These metrics were analyzed using the different tests illustrated in Figs. 6.7, 6.8, 6.9, 6.10, 6.11 to de- termine whether the signal was performing as intended. Fig. 6.7 shows the distortion behavior of the BD PWM signal for sinusoidal ampli- tude input values exceeding 0 dBFS, to verify whether the signal clips as expected when overloaded. The upper plot shows THD and THD+N in dB versus input am- plitude (dBFS), while the lower plot presents the THD and THD+N in percentage versus input amplitude (dBFS). The test was performed for the BD PWM when driven by a non-quantized sinusoidal with fundamental frequency f0=1 kHz as in- Figure 6.6: PSD of the BD PWM driven by both a non-quantized and a 16-bit quantized sinusoidal input with f0= 4410 Hz. 39 6. Method Figure 6.7: THD and THD+N of the BD PWM signal driven by a non-quantized sinusoidal input with f0=1 kHz, for input amplitudes ranging from 0 to 6 dBFS. put. The input amplitude of the sinusoidal was swept from 0 to 6 dBFS. Already at 0 dBFS the signal starts clipping, causing a linear increase in both THD and THD+N until 1 dBFS where it reaches an approximately constant value. Fig. 6.8 visualizes the amount of THD and THD+N of the BD PWM when driven by a non-quantized sinusoidal with f0=1 kHz as input, for input amplitude levels of the sinusoidal ranging from -120 to 0 dBFS. It is evident that at low input amplitude levels, THD+N exceeds 2000 %, indicating a very high level of distortion due to noise. Fig. 6.9 shows the THD and THD+N of the BD PWM when driven by a 16-bit Figure 6.8: THD and THD+N of the BD PWM signal driven by a non-quantized sinusoidal input with f0=1 kHz, for input amplitude levels ranging from -120 to 0 dBFS. 40 6. Method Figure 6.9: THD and THD+N of the BD PWM signal for a 16-bit quantized sinusoidal input with f0=1 kHz, with input amplitude levels ranging from -120 to 0 dBFS. quantized sinusoidal, with f0=1 kHz as input, for input amplitude levels of the sinu- soidal ranging from -120 to 0 dBFS. As noted in section 2.3.1, the dynamic range for a 16-bit system is around 96 dB. The plot shows that from values below -96 dBFS the THD and THD+N values are constant, indicating that the system is unable to accurately represent signals below its dynamic range. To visualize the THD and THD+N levels of the BD PWM signal at different fun- damental frequencies of the sinusoidal, a frequency sweep was performed from 20 to 9 kHz driven by a non-quantized sinusoidal input with input amplitude of -5 dBFS shown in Fig. 6.10. The upper limit of 9 kHz was chosen to ensure that the second harmonic of the signal remained within the audible frequency range (20 Hz Figure 6.10: THD and THD+N of the BD PWM signal versus frequency from 20 to 9 kHz with a non-quantized sinusoidal input with -5 dBFS input amplitude. 41 6. Method to 20 kHz). Signals with fundamental frequencies of 10 kHz and above were omitted because the second harmonic would exceed the upper limit of the audio frequency range, making them irrelevant for this work. The same frequency sweep was performed for the BD PWM signal when driven by a 16-bit quantized sinusoidal input with -5 dBFS input amplitude, shown in Fig. 6.11. One notable difference is that the THD for the non-quantized signal starts at approximately -165 dB at 20 Hz, while for the quantized signal it starts at around -115 dB at 20 Hz. Additionally, the THD values are slightly lower at all frequencies for the non-quantized signal. Figure 6.11: THD and THD+N of the BD PWM signal versus frequency from 20 to 9 kHz with a 16-bit quantized sinusoidal input with -5 dBFS input amplitude. 42 6. Method 6.2.5 Implementation of Dead Time Control in BD PWM In order to implement dead-time control in the BD PWM the principles discussed in section 3.3.1, were applied. Figs. 6.12a and 6.12b illustrate the implementation of dead time on the A- and B-sides, respectively. Since the PWM clock frequency was set to fPWM = 90.3168 MHz, the corresponding minimum dead time is approx- imately tdead,min = 1/fPWM ≈ 11 ns. (a) Zoomed view of added dead time on A-Side with PMOS1 and NMOS1 (b) Zoomed view of added dead time on B-Side with PMOS2 and NMOS2 Figure 6.12: Implementation of Dead time on A- and B-Sides. Zoomed-in views illustrating the added dead time between the high-side (PMOS1/PMOS2) and low- side (NMOS1/NMOS2). 43 6. Method 6.2.6 Dither Noise Generation in Quiescent Power Measure- ment The quiescent power consumption of the power amplifier, PQ, is in this work defined as the power loss when the amplifier is in a quiescent state and calculated using (2.15). This represents a scenario when there is no audio input signal present, only background noise with an amplitude bounded within ± 1 LSB or ± 1/(215 − 1). To measure the quiescent power consumption of the power amplifier, the theory regarding single sided BD modulation was employed as introduced in section 3.2.1. Instead of using two sinusoidal input signals, two dithering triangular noise signals were used, visualized in Fig. 6.13. They were generated by summing two indepen- dently uniform random signals. Fig. 6.14 shows the power spectral density of the BD PWM signal when driven with triangular noise. The spectrum primarily consists of the ∆Σ shaped noise floor and the PWM switching harmonics, at the switching frequency. No fundamental harmonic components can be seen, as the input only consists of triangular noise. Figure 6.13: Time-domain representation of the triangular noise and the inverted triangular noise. 44 6. Method Figure 6.14: PSD of the BD PWM signal driven by triangular noise. 6.3 Design and Simulation of the Class D Power Amplifier in LTspice For the circuit simulations of the Class D power amplifier, LTspice was chosen due to its simplicity, efficiency and relatively accurate modeling of circuit components. The MOSFET gate control signals were first generated in Matlab, resampled and then imported into LTspice as voltage sources. The selected MOSFETs for the PCB, namely PMDXB950UPEL and PMDXB290UNE could not be imported into LTSpice [42, 43]. Thus, a suitable MOSFET pair with similar switching parameters parameters was found, as shown in Table 6.2. For the PMOS pair, Si1555DLP was selected, and Si1555DLN was selected for the NMOS pair [44]. Fig. 6.15 visualizes the output stage of the Class D power amplifier implemented in LTspice using an H-bridge circuit, with the corresponding component values listed in table 6.3. It was designed without an output filter, using a series RLC circuit as discussed in section 3.3.2, which consisted of an inductor L1 or L2 in series with its internal serial resistance RL, connected in series with the piezoelectric actuator CPiezo. Since the piezoelectric actuator has both capacitive and resistive character- istics it was modeled using both a capacitor and a resistance. In technical literature regarding Class D power amplifiers with piezoelectric actuators, the piezoelectric Table 6.2: Comparison of the switching parameters of the MOSFETs on the PCB and in LTspice. MOSFET Qg (Charge) RDS(on) Si1555DL_N 8 × 10−10 C 0.58 Ω Si1555DL_P 1.5 × 10−9 C 0.63 Ω PMDXB950UPEL 0.9 × 10−10 C 0.32 Ω PMDXB290UNE 1.8 × 10−9 C 1.00 Ω 45 6. Method − +V1 RSupply VrailA R1 C1 R2 C2 − +V2 VrailB RSupply R3 C3 R4 C4 Si1555DLP VrailA Si1555DLN RGate N1Gatesignal RGate P1Gatesignal RL L1 CPiezo L2 RL VrailB RGate N2Gatesignal RGate P2Gatesignal Si1555DLN Si1555DLP Figure 6.15: Output power stage of the Class D power amplifier implemented as an H-bridge circuit and simulated in LTspice. actuator typically has a capacitance value between 1 and 4 µF as listed in Table 8.1. Thus, the capacitance CPiezo was selected as 1 µF, with a serial resistance of 10 mΩ, and the chosen inductance of the inductors L1 and L2 were selected as 47 µH with a serial resistance of 0.47 Ω. This configuration of component values in the series RLC circuit, resulted in a resonance frequency of 23.215 kHz as calculated by (3.4), and a Q factor of approximately 12.03 determined by (3.5). The bode plot depicting the magnitude and phase response over the piezoelectric actuator is shown in Fig. 6.16. To simplify the simulations the output stage was designed using two separate voltage sources VrailA and VrailB as shown in Fig. 6.15, instead of a single supply as on the PCB. Each voltage source included two series low-pass RC filters and a series resistor Table 6.3: List of circuit components and their values. Component label Value R1, R3 0.3 Ω R2, R4 1 mΩ L1, L2 47 µH CPiezo 1 µF RL 0.245 Ω C1, C3 100 µF C2, C4 10 µF V1, V2 3.3 V RSupply 10 mΩ RGate 10 mΩ 46 6. Method Figure 6.16: Frequency response of the RLC filter. RSupply. The first filter had a cut-off frequency of around 5.3 kHz, and consisted of R1 and C1 on VrailA and R4 and C4 on VrailB . The second filter with a cut-off of around 16 MHz, consisted of R2 and C2 for VrailA and R3 and C3 for VrailB . 6.4 Design of the Output Stage PCB For the development and design of the output stage PCB, KiCad was used due to its simplicity to use and the arrangement of features. Fig. 6.17 presents the schematic of the PCB, where the selected circuit components and their values are listed in Table 6.4. Ceramic multilayered decoupling capacitors, C1 − C6 were placed on the PCB to minimize parasitic inductance and noise. In series with each microcontroller output pin, a 0 Ω ballast resistor (R1 − R7) with a generic footprint was placed, allowing for switching to a different resistance value if necessary. On the 2-layered PCB, the top layer was connected to VDD and the bottom layer was connected to ground GND. Table 6.4: List of selected circuit components and their values. Component Label Value GRT188R61H105KE13D C1, C4 1 µF GRM188R6YA106MA73J C2, C5 10 µF GRM188R60J476ME01D C3, C6 47 µF PMDXB950UPEL Q1 - PMDXB290UNE Q4 - LPS6235-223MRC L1, L2 47 µH Resistor R1, R2, R3, R4, R5, R6, R7, R8 0 Ω 47 6. Method Figure 6.17: Schematic of the PCB layout designed in KiCad. 6.5 Microcontroller Implementation Next step was to implement the DSP system tested in MATLAB on the micro- controller. Some of these steps were carried out in parallel with the MATLAB coding. The coding on the LPC55S69 was carried out on its designated devkit LPCXpresso55S69-EVK. 6.5.1 Coding The approach to implement the second order ∆Σ modulator on the microcontroller was similar, but there were some key differences. For example, the microcontroller uses the C language, and the specific data type have a great impact when it comes to timing and execution of the program. The first step was to translate the code from MATLAB to C. The second order ∆Σ modulator structure, along with the interpolation stage was implemented, and the FIR filter coefficients were imported along side a sinusoidal test signal. The test signal was a sinusoidal tone at 400 Hz, rescaled to an 8-bit integer. 6.5.2 I2s There are two ways of implementing I2s on the LPCXpresso55S69-EVK. Either using dedicated pins or by using the audio stream line located at the top of the controller. First, an attempt was made to use the pins to receive audio, by generating an audio wave using an audio analyzer. However, this was unsuccessful and some errors in the microcontroller could not be resolved. Therefore, a demo using the audio jack was adopted. Using this code, audio was received and handled using a ping-pong type buffer. However, due to time constraints, a sinusoidal tone was imported in order to start with PWM generation. 48 6. Method 6.5.3 PWM The microcontroller has several ports that can be used to output PWM. For this project, four pins are needed, one for each MOSFET, and eight are preferred in order to generate a two times higher current to drive the gates without using a gate driver circuit. Luckily, the LPCXpresso55S69-EVK has 9 different PWM output ports, and all can be controlled using a single timer, SCT0. To find which pins can be used in the devkit for PWM you first have to look up the SCTimer output pins of the sctimer, in Table 501 in [45]. Following this, you have to go into the schematic diagram at sheet 3 of [46] and see where the pins are located in