Investigation of Bridgeless Power Fac- tor Correction Topologies for 3 kW Op- eration Amer Mesic Oscar Arvering Walldén Department of Electrical engineering CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2021 Master’s thesis 2021 Investigation Of Bridgeless Power Factor Correction Topologies For 3 kW Operation Amer Mesic Oscar Arvering Walldén Department of Electrical Engineering Division of Electric Power Engineering Chalmers University of Technology Gothenburg, Sweden 2021 Investigation uof Bridgeless Power Factor Correction Topologies for 3 kW Operation Amer Mesic & Oscar Arvering Walldén © Amer Mesic & Oscar Arvering Walldén, 2021. Supervisor: Fredrik Persson, Ericsson Examiner: Torbjörn Thiringer, Chalmers University of Technology Master’s Thesis 2021 Department Electrical Engineering Division of Electrical Power Engineering Chalmers University of Technology SE-412 96 Gothenburg Telephone +46 31 772 1000 Typeset in LATEX Gothenburg, Sweden 2021 iii Abstract Power Factor Correction (PFC) circuits are widely used today in switch mode power supplies. The purpose of these circuits is to improve the quality of power drawn from the grid by reducing the reactive power drawn by the application as well as reducing the harmonic content of the current. Conventional PFCs consist of a bridge rectifier that rectifies the AC voltage to DC which is then followed by a boost converter which shapes the input current of the converter to be in phase with the input voltage and thereby obtaining a power factor close to unity. The aim of this project was to inves- tigate PFC topologies which eliminate the bridge rectifier to increase the efficiency and improve the thermal performance of the converter. First, a literature study was conducted to select the three most suitable topologies for 3 kW operation. The selected topologies are the Semi-Bridgeless Boost PFC, Bridgeless Interleaved Boost PFC and Totem-Pole Boost PFC utilizing Gallium Nitride transistors. Thereafter a performance analysis of each topology was carried out using Matlab and Simulink simulations. The parameters of interest are efficiency, power factor, input current ripple, inrush current and thermal performance as well as the component count and complexity of the converters. The Bridgeless Interleaved PFC was found to be the topology with leading perfor- mance in all parameters of interest. The peak efficiency achieved was 97.86 percent with Totem pole closely thereafter at 97.55 percent. All the topologies achieved a power factor near unity. Due to the inherent ripple cancellation of the Bridgeless Interleaved PFC, this topology had the lowest input current ripple as well as the lowest total harmonic distortion for full load operation. iv Acknowledgements We would like to formally show appreciation to our supervisor at Ericsson, Fredrik Persson, for the guidance and encouragement throughout the work. We would also like to show our utmost gratitude to Michael Heitmann for accepting our application and giving us the opportunity to carry out this thesis at Ericsson. Last but not least would we like to thank our examiner and supervisor at Chalmers University of Technology, Torbjörn Thiringer for the feedback and technical support throughout the project. v Contents 1 Introduction 2 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Sustainable Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Theoretical Background 5 2.1 AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Power Factor Correction . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . 6 2.1.3 AC/DC Conversion . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 Modes of Operation for Power Converters . . . . . . . . . . . 8 2.1.4.1 Continuous Conduction Mode (CCM) . . . . . . . . 8 2.1.4.2 Discontinuous Conduction Mode (DCM) . . . . . . . 9 2.1.4.3 Critical Conduction Mode (CrCM) . . . . . . . . . . 10 2.2 Active Power Factor Correction Topologies . . . . . . . . . . . . . . . 11 2.2.1 Active Boost PFC . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Interleaved Boost PFC . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Bridgeless Power Factor Correction Topologies . . . . . . . . . . . . . 13 2.3.1 Semi-Bridgeless PFC . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1.1 Converter Operation for Positive Half Cycle . . . . . 14 2.3.1.2 Converter Operation for Negative Half Cycle . . . . . 15 2.3.2 Bridgeless Interleaved Boost PFC . . . . . . . . . . . . . . . . 16 2.3.2.1 Converter Operation for Positive Half Cycle . . . . . 17 2.3.2.2 Converter Operation for the Negative Half Cycle . . 18 2.3.3 Totem-Pole Bridgeless Boost PFC Utilizing GaN Transistors . 20 2.3.3.1 Converter Operation for Positive Half Cycle . . . . . 21 2.3.3.2 Converter Operation for Negative Half Cycle . . . . . 22 2.4 Analytical Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.1 Semi-Bridgeless PFC and Bridgeless Totem-pole PFC . . . . . 24 2.4.2 Bridgeless Interleaved Boost PFC . . . . . . . . . . . . . . . . 27 2.5 Small Signal Models of Bridgeless PFC Topologies . . . . . . . . . . . 28 2.5.1 Semi Bridgeless and Bridgeless Totem-pole Boost PFC . . . . 28 vi Contents 2.5.2 Bridgeless Interleaved Boost PFC . . . . . . . . . . . . . . . . 31 3 Simulations 33 3.1 Modeling of Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.1 Semi-Bridgeless Boost PFC . . . . . . . . . . . . . . . . . . . 33 3.1.2 Bridgeless Interleaved Boost PFC . . . . . . . . . . . . . . . . 34 3.1.3 Bridgeless Totem-Pole Boost PFC utilizing GaN Transistors . 35 3.2 Implementation of the Control Systems . . . . . . . . . . . . . . . . . 36 3.2.1 Tuning of the Controllers . . . . . . . . . . . . . . . . . . . . . 37 3.2.2 Simulink Implementation and System Testing . . . . . . . . . 39 3.2.2.1 Semi-Bridgeless Boost PFC . . . . . . . . . . . . . . 39 3.2.2.2 Bridgeless Interleaved Boost PFC . . . . . . . . . . . 41 3.2.2.3 Bridgeless Totem-Pole Boost PFC Utilizing GaN tran- sistors . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 Results 45 4.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.1 AC Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.2 DC Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 Harmonic Distortion and Power Factor . . . . . . . . . . . . . . . . . 48 4.3 Input Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4 Inrush Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.1 AC Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.2 DC Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 Component Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5 Conclusion 52 6 Discussion and Future Work 53 References 54 1 1 Introduction 1.1 Background Switching mode power supply (SMPS) units are widely used to convert between different voltage levels. At the input stage of power supply units which are used for AC/DC applications, a diode bridge rectifier is often used to rectify the AC voltage connected to the DC/DC converter. The utilization of the bridge and the DC/DC converter will lead to a non-optimal power factor as well as current harmonics being injected both into the grid and the circuit. To increase the power factor in the SMPS, a Power Factor Correction (PFC) circuit is commonly used between the rectifier stage and the DC/DC converter. There are different types of PFC circuits but a commonly used topology is a Boost-converter circuit which is connected in between the bridge rectifier and the DC/DC converter. By adjusting the duty cycle in the Boost circuit, the current wave form can be adjusted so that it is in phase with the voltage waveform. This will lead to high power factor which is desired. The bridge rectifier will be one of the main sources of losses in this setup. This is due to the conduction losses in the diodes of the bridge rectifier. Due to this it is of interest to investigate different types of bridgeless topologies for power factor correction which eliminate the bridge rectifier in order to further reduce the losses in the SMPS. 1.2 Aim The aim of this project is to investigate different topologies of power factor correction circuits which eliminate the need for the diode bridge rectifier at the input to further increase the efficiency and thermal performance of the PFC. The PFC should be able to operate with 86-264 VAC as well as 260-400 VDC input voltage. The output voltage of the PFC should be 405 VDC and the output power should be 3 kW. 2 1. Introduction 1.3 Problem Description Operating requirements for the PFC are given in the table 1.1. Table 1.1: Specifications for the Power Factor Correction circuit Input voltage 86-264 VAC & 260-400 VDC Input frequency 47-63 Hz Nominal output voltage 405 V Hold up time 20 ms Output power 3 kW A literature study of bridgless PFC topologies is conducted and the most suitable toplogies are selected and investigated in detail. The selection of suitable topologies is based on following parameters: • Does the topology meet the operating requirements given in table 1.1? • Power Factor • Efficiency • Total Harmonics Distortion (THD) • Input current ripple • In-rush current • Electromagnetic Interference • Complexity • Component Count Simulations of selected toplogies are conducted and comparisons of different topolo- gies is done based on the above mentioned parameters. 1.4 Scope In this project the performance of different bridgeless PFC topologies is investigated with help of calculations and computer simulations. The goal of the project is not to build a physical bridgeless power factor correction circuit or any kind of converter, rather to investigate which bridgeless PFC topologies are most suitable for the above mentioned operating requirements. 1.5 Sustainable Aspects One of the greatest challenges the human species have to face in the coming years is the challenge of global warming. In order to tackle the effects of global warming, 189 countries have joined the Paris agreement where the goal is to limit the global temperature rise at 2 °C during this century [1]. The world needs to make the transition from the use of fossil fuels to more renewable energy sources such us wind and solar in order to reduce the amount of CO2 released into the atmosphere, but this 3 1. Introduction transition is a big one and will take long time to achieve. Another way to decrease the amount of the CO2 released into the atmosphere is to decrease the consumption of electrical energy. This can be done by further improving the efficiency of the electrical devices and converters. The power factor correction circuits are used in AC/DC converters to improve the power factor and total harmonics distortion of the current drawn from the grid. With the use of PFC circuits, greater efficiency of the AC/DC converter can be achieved. By finding ways to get rid of the diode bridge rectifier which can be seen in the most common Active Boost PFC topology, the efficiency of the PFC stage can be further improved. Due to the wide use of PFC circuits and a necessity to convert AC voltage to DC in many cases before use, it is important that the PFC circuits have high efficiency. In this project different bridgeless PFC topologies which increase the efficiency of the PFC are investigated. By improving the efficiency of the PFC stage, less power needs to be consumed which means less CO2 needs to be released into the atmosphere. 4 2 Theoretical Background 2.1 AC/DC Converters The dominant way of transmitting electrical power is in the form of a high voltage alternating current (AC). The advantage of AC compared to direct current (DC) transmission is lower transmission costs and a simple way of converting between different voltage levels with the help of transformers. Even though most of the power is transmitted in the form of AC, a large part of the power consumption is done using DC power. Due to this fact there is a necessity to efficiently convert the transmitted AC power to DC before use. AC/DC converters are used to accomplish this task, a block diagram of a typical AC/DC converter is shown in the figure 2.1. From the block diagram, it can be seen that the AC voltage is first converted to varying DC voltage using a a diode bridge rectifier, thereafter a power factor correction (PFC) stage is found where the current waveform is shaped to be in phase with the voltage waveform. After the PFC stage, a DC/DC converter will convert the voltage to a required voltage level for the load. This chapter will introduce some of the necessary terminology needed to understand the AC/DC converters with emphasis placed on the PFC stage. Figure 2.1: Block diagram of an AC/DC converter . 5 2. Theoretical Background 2.1.1 Power Factor Correction Most of the electrical equipment in use today is in some way connected to the grid, either constantly or for some duration of time. Such equipment ranges from phone chargers that consume a couple of Watts of power to charging stations for electrical vehicles which consume a couple of kW and beyond. When electrical equipment is connected to the grid it will be represented as a complex load. In many cases this load will draw a current that is not in phase with the input voltage. This will lead to consumption of both active and reactive power from the grid. The definition of power factor is the ratio between the usable active power (P) and the apparent power (S) which is the sum of active and reactive power (Q), PF = P |S| (2.1) A power factor which is equal to one indicates that the voltage and current waveforms are in phase with each other and that only active power is consumed. When the power factor is below one, it means that the voltage and current waveforms are displaced from one another and that both active and reactive power is consumed. The reactive power is not usable but the consumption of it will lead to circulating currents in the system which in turn lead to higher currents drawn from the grid. This means more losses and a need for example thicker cables that can handle higher currents. To minimize the reactive power and therefore minimize the total apparent power consumed from the grid, power factor correction circuits are utilized. These circuits shape the current drawn from the grid to be in phase with the voltage. They are also used to reduce the harmonic distortion of the input current which will lead to higher efficiency and lower distortions in the grid. In recent years more strict limits have been placed on the amount of harmonics all electrical equipment can inject to the grid. In the European Union, electrical systems are required by law to meet the requirements which are stated in EN 61000-3-2 which is a standard for the limitation of harmonic current emissions. Power factor correction circuits are critical when it comes to meeting these requirements. 2.1.2 Total Harmonic Distortion Total harmonic distortion (THD) is the measure of the amount of distortions in a specific signal. It is defined as the ratio between the sum of all of the harmonic components and the fundamental component of the signal. The expression is THD = √∑∞ n=2 I 2 n I1 (2.2) The current harmonic components will not contribute to the real power drawn from the sinusoidal source [2]. The THD and the power factor can then be related to each other with the following expression PF = cosθ√ 1 + THD2 −→ cosθ = Displacement Power Factor (2.3) 6 2. Theoretical Background 2.1.3 AC/DC Conversion One of the simplest ways of converting AC voltage to DC is with the help of a bridge rectifier with a capacitive filter at the output. The bridge rectifier consists of four diodes which convert the AC input waveform from a varying signal with negative and positive pulses to two consecutive DC pulses. This new signal is then fed to the smoothing capacitor that is in parallel with the load. The capacitor is charged during the rise of a pulse and discharged during the fall but is discharged slower as to keep the voltage at a steady level. This is what generates the DC voltage on the output. The base rectifier circuit can be seen in figure 2.2. Figure 2.2: Diode bridge rectifier connected to a smoothing capacitor and the load The advantage of this circuit is the low cost and complexity but it has some inherent issues when it comes to the quality of current drawn form the AC source. What will happen in this case is that the current will flow only when the input voltage is higher than the voltage across the filter capacitor. This will result in a non-sinusoidal current waveform with low power factor and a high harmonic distortion, see figure 2.3 7 2. Theoretical Background Figure 2.3: Input voltage and current waveforms of the circuit in figure 2.2 For this reason PFC circuits are used in order to improve the quality of the power drawn from the grid. There are many possible PFC topologies, these are divided into passive and active PFCs. Passive PFC topologies do not use any control loops but rather use passive components such as inductors in combination with the bridge rectifier and the filtering capacitor to improve the power factor and current harmon- ics. One simple and popular example of a passive PFC is to place an inductor in series with the AC source just before the bridge rectifier. This will lead to a im- provement in the power factor and harmonic distortion in the input current. Passive PFC ciruits are simple and easy to implement but they are not suitable for high power applications due to the size increase of the inductor. At high power levels the inductor on the AC input has to be very large, which will increase the size and losses of the converter. Also it is difficult to achieve high power factor for applica- tions which need to work in a range of different input voltages [3]. Due to these reasons the emphasis in this project will be put on active PFC topologies. 2.1.4 Modes of Operation for Power Converters For active PFC topologies the power is controlled by transistors that are in turn controlled by a control circuit. The operation of these switches determine the shape of the current waveforms and the most common modes of operation are presented below. 2.1.4.1 Continuous Conduction Mode (CCM) When the converter is in CCM mode of operating the inductor current will be continuous. This means that the current coming from the grid and going through the inductors won’t be zero with the exception of the zero crossings. The waveform can be seen in figure 2.4. This results in a low dI/dt over both the inductors and the switches since the current doesn’t have to rise from zero to the reference. This mode of operation is therefore more suitable for higher power levels. A drawback 8 2. Theoretical Background with this mode is that since the current doesn’t reach zero, the switches are hard switched. Hard switching is when the drain-source voltage overlaps with the drain current. This results in higher switching losses. Figure 2.4: Wave forms of currents during CCM 2.1.4.2 Discontinuous Conduction Mode (DCM) Discontinuous conduction mode is as the name implies when the current coming from the grid and going through the inductors is discontinuous, meaning that during a voltage period of the grid, the current is switched from zero to the level needed multiple times. The waveform can be seen in figure 2.5. As opposed to CCM this results in high dI/dt over the inductors and switches. This also means that the switches can be soft switched lowering the switching losses. DCM has higher electromagnetic interference than CCM which is very apparent when utilized for high power levels. Figure 2.5: Wave forms of currents during DCM 9 2. Theoretical Background 2.1.4.3 Critical Conduction Mode (CrCM) The critical conduction mode or boundary conduction mode as it is also called, is when the current average is achieved by the switching current reaching a sufficiently high level but then switched completely off for a very brief time. Contrary to DCM the current doesn’t stay at zero level for a significant amount of time instead only stays down long enough to achieve soft switching and minimize switching losses. The waveform can be seen in figure 2.6. As for the DCM mode the CrCM will also have higher EMI and lower switching losses. Figure 2.6: Wave forms of currents during CrCM 10 2. Theoretical Background 2.2 Active Power Factor Correction Topologies Active PFC topologies improve the power factor by using active components such as transistors and diodes in combination with passive components such as inductors and capacitors. Some sort of control feedback loop is used to shape the input current to be in phase with the supply voltage. There are many possible active PFC topologies to choose from. These include PFC topologies that are based on Buck, SEPIC, Flyback, CUK and Buck-Boost converters but the most popular active PFC topologies for high power are based on some kind of Boost converter topology. Since the PFC circuit in this project requires a high power and a steady high voltage level, systems derived from the boost topology are chosen to be investigated. In the text below the operating principles for different active PFC topologies based on the Boost converter will be given. 2.2.1 Active Boost PFC The Active Boost PFC consists of a diode bridge rectifier at the input followed by a boost stage containing an inductor, a diode, a switch and lastly an output filter capacitor. The schematic of the active boost PFC can be seen in figure 2.7. The diode bridge will rectify the sinusoidal input to a positive sinusoidal half wave voltage and by adjusting the duty cycle of the switch, the current waveform can be placed in phase with the voltage waveform, making it possible to obtain a power factor close to unity and to improve the total harmonics distortion of the input current. This circuit is popular due to its simplicity and low cost but one of its drawbacks is the diode bridge in the front end. The conduction losses of the bridge diodes will be responsible for a large part of the losses inside the boost PFC. This will lead to a lower efficiency of the circuit but will also cause some issues with the thermal management when it comes to high power application. Due to these issues, the active boost PFC should only be used for powers up to 1kW [4]. Figure 2.7: Schematic of the active boost PFC 11 2. Theoretical Background 2.2.2 Interleaved Boost PFC The interleaved boost PFC consists of a diode bridge rectifier at the input stage, followed by two boost converters connected in parallel and a storage capacitor at the output. The circuit schematic of the interleaved boost PFC can be seen in figure 2.8. The diode bridge rectifies the input sinusoidal voltage to a varying DC voltage. With help of the boost stage and by adjusting the duty cycle of the transistors the current waveform can be placed in phase with the voltage waveform. Finally the output capacitor will filter out the AC component and provide the load with a DC voltage. The two boost converters in the interleaved PFC will operate 180 degrees out of phase [5] and the input current will be the sum of the two currents flowing through inductor L1 and L2. Due to the interleaving and the fact that the inductor currents flowing through L1 and L2 are out of phase, the ripple current flowing through the inductors tend to cancel each other out, leading to a lower input current ripple [5]. Also the advantage of interleaving two boost converters is that it makes the converter more suitable for high power applications. When the interleaving is utilized the current flowing through the transistors will be lower than in the case of the conventional active boost PFC [6]. This will lead to better performance of the converter when it comes to efficiency and thermal management which is important at high power ratings. Another result of interleaving is the size reduction of both the boost inductors as well as the EMI filter [6]. The output capacitor high frequency ripple is also reduced as a result of interleaving. Although the Interleaved Boost PFC is more suitable for higher power application and has better performance than the conventional active boost PFC, it still has the drawback that come with the use of a diode bridge rectifier at the input. The bridge will cause additional losses and problems with thermal management in the converter. In the following section, PFC topologies which eliminate the input diode bridge rectifier will be discussed. Figure 2.8: Schematic of Interleaved boost PFC 12 2. Theoretical Background 2.3 Bridgeless Power Factor Correction Topolo- gies To solve the problem of heat management and to further increase the efficiency of the PFC, bridgeless topologies can be used. Bridgeless PFC topologies eliminate the diode bridge rectifier at the AC input which reduces number of diode forward drops in the path of the current which flows from the AC source to the load. This will result in lower conduction losses in the circuit. As there are many different bridge- less PFC topologies to choose from, it was necessary to conduct a literature study to determine which topologies are most suitable for the application. The operating requirements for the PFC application as well as other important parameters that need to be considered when selecting suitable topologies can be seen in section 1.3. From the literature study it was found that most suitable bridgeless PFC topologies are in some way based on the boost converter topology. This is the case for two reasons, the first reason is that for this project one of the requirements was that the output voltage of the PFC should be higher then the input voltage and this can be achieved with the help of a boost converter. The second reason was that the input current of the boost converter operated in CCM has low conducted elec- tromagnetic interference when compared to other topologies such as buck-boost or buck converter for high power operation [6]. Three topologies were selected, which are thought to be the most suitable for the given application. These topologies are the Semi-Bridgeless Boost PFC, the Bridgeless Interleaved Boost PFC and the Totem-pole PFC utilizing Galium Nitride transistors. These topologies were found suitable because they can operate at high output power levels > 3 kW, have a good efficiency η > 92%, yield high power factor, have low input current ripple and have low electromagnetic interference. Other topologies which were investigated include bridgless PFC topologies based on SEPIC, CUK, Buck, Buck-Boost and Flyback converters. Some other bridgeless boost topologies which were investigated include the Bridgeless boost PFC with a bidirectional switch, the Three level Bridgeless boost PFC and Bridgeless Psuedo-boost PFC. These topologies were found to be inferior compared to the three chosen topologies in terms of possibility to handle high output power, efficiency, EMI, component count and/or complexity. In the text below the operational principles of Semi-Bridgeless Boost PFC, Bridgeless In- terleaved Boost PFC and Totempole PFC utilizing Gallium Nitride transistors will be presented. 2.3.1 Semi-Bridgeless PFC To further improve the efficiency and thermal performance of the Active Boost PFC the diode bridge rectifier at the input needs to be removed. One topology which manages to remove the input diode bridge rectifier and increase the efficiency of PFC circuit is the Semi-Bridgeless Boost PFC. This topology consists of two Boost converters where one operates during the positve half cycle of the AC input and the other one for the negative half cycle. Two additional slow diodes D2 and D4 are introduced to connect the ground to the neutral terminal and provide a return path 13 2. Theoretical Background for the current, see figure 2.9. The addition of the return diodes prevent the input voltage from floating and rather being referenced to ground [7]. As a result, the input voltage sensing is made easier because a voltage divider can be used instead of a low frequency transformer or optocoupler [8]. Another benefit of the return diodes is that the EMI performance of the PFC will be improved. As mentioned these diodes provide the return path for the current but all of the current will not always flow through them. A large portion of the current will return through the body diode of the non-switching MOSFET. The reason this occurs is due to the low impedance of the inductor at line frequency [8]. How large portion of the current that flows through the body diode and the return diodes is determined by the component characteristics. The double inductors reduce the dV/dt from the switches making the signal more stable and less prone to peaking. Two inductors help with thermal management since they split the input and are only active during one half cycle respectively. This circuit is relatively simple to control and drive because both transistors can be driven with the same gate signal. This topology is suited for high power application >1kW but due to the higher component count it will have higher cost when compared to the conventional Active Boost PFC. The schematic of the Semi-Bridgeless PFC can be seen in figure 2.9 and detailed operation of the PFC for both the positive and negative half cycles will be presented in the text below. Figure 2.9: Schematic of the semi bridgeless boost PFC 2.3.1.1 Converter Operation for Positive Half Cycle The Semi-Bridgeless PFC converter operation for the positive half cycle can be divided into two different states, when the transistor M1 is conducting and when it is not. When it isn’t conducting as can be seen in figure 2.10, the source and inductor L1 supplies the load and capacitor with current. The current flows through D5 and returns through D4 to the source. In the other state M1 is conducting and the inductor, L1 is charging whilst the capacitor is discharged to keep the load voltage steady. The current flows through M1 and D4 to charge the inductor. 14 2. Theoretical Background Figure 2.10: Converter operation for positive half cycle 2.3.1.2 Converter Operation for Negative Half Cycle Just as for the positive half cycle there are two different states of operation for the negative half cycle. The first one being when the switch M2 isn’t conducting and the current is discharged from inductor L2 and the supply to the output and capacitor. The current flows through and from the inductor, through the diode D6 and then back again through the return diode D2. The other state is when the switch is conducting and the inductor, L2 is charged with current flowing through the transistor M2 and returning through D2 whilst the capacitor is discharged to the load to keep the voltage at the desired level. Figure 2.11: Converter operation for negative half cycle 15 2. Theoretical Background Design challenges The Semi-Bridgeless PFC is a promising topology with its advantages but there are some challenges that need to be overcome in the design stages. Some of these challenges are mentioned below. Reverse recovery One of the challenges with this topology is that the output diodes will cause severe reverse-recovery problems which occur due to the high output voltage and high diode forward current [6]. The reverse-recovery of the output diodes will be more signifi- cant during high switching frequencies and can lead to additional turn-on losses and higher EMI noise. For this reason the reverse recovery can be a bottleneck when it comes to high switching frequencies [9]. In order to improve the reverse recovery of the output diodes, Silicon Carbide (SiC) Schottky Diodes which have no reverse recovery charge can be used. Current Sensing Current sensing for this topology is relatively complex. Because all of the current will not return thorough the return diodes it is not possible to use a single shunt resistor to measure the current like in the case of the Active Boost PFC. One way of measuring the current which is mentioned in [10] is to use four current transform- ers to measure the current in both switches as well as the current flowing through the output capacitor and the load. These currents are then summed together and applied to a shunt resistor which is used to measure the total current. This method will lead to a more complex control circuit and will also need some sort of reset network which will demagnetize the current transformers [10]. This can be simpli- fied with a dedicated controller IC such as UCC28070 which will eliminate the need for modification of the sensing circuit. Another way is to use a differential mode amplifier to sense the current in the front of the PFC inductor. 2.3.2 Bridgeless Interleaved Boost PFC The Bridgeless Interleaved (BLIL) Boost PFC is similar to the Interleaved Boost PFC but the diode bridge rectifier at the input is removed. The number of semicon- ductors in this topology will be the same as in the Interleaved Boost PFC but two additional transistors and two fast switching diodes will replace the four slow diodes of the input bridge of the Interleaved PFC. The circuit schematic for the Bridgeless Interleaved Boost PFC can be seen in the figure 2.12. This topology will retain the advantages of the Interleaved PFC such as good thermal performance, low input current ripple, good EMI and high efficiency. Due to the elimination of the input bridge and interleaving of four boost converters instead of two, an improved effi- ciency and better thermal performance can be obtained which makes this topology suitable for high power applications above 3 kW [5]. The detailed operation of BLIL Boost PFC for both the positive and negative half cycles will be presented in the text below. 16 2. Theoretical Background Figure 2.12: Schematic of Bridgeless Interleaved PFC 2.3.2.1 Converter Operation for Positive Half Cycle During the positive cycle of the AC input voltage, the switches SW1 and SW2 will be conducting. The current will then flow from the input through the inductors L1, switches SW1 and SW2 and finally through the inductor L2 before returning to line. At this time the current will magnetize the inductors resulting in energy being stored within them. When the switches SW1 and SW2 are turned off, the stored energy inside the inductors will be released in form of a current which will then flow through the diode D1, the load and finally through the body diode of the switch SW2 before returning to the line. A similar operation will happen for switches SW3 and SW4 but it will be delayed with 180 °. When switches SW3 and SW4 are turned on the current will flow from input through the inductor L2 and switches SW3 and SW4 finally making its way through the inductor L4 before returning to the line. The energy will be stored in these inductors during this time and when the SW3 and SW4 are turned off this energy will be released in form of a current that flows through diode D3, the load and the body diode of the SW4 before returning to the line. The current paths for the positive cycle operation can be seen in figure 2.13. Figure 2.13: Positive cycle operation for Bridgeless Interleaved Boost PFC 17 2. Theoretical Background 2.3.2.2 Converter Operation for the Negative Half Cycle During the negative half cycle the switches SW1 and SW2 are turned on and the current will flow through the inductor L3, switches SW1 and SW2 and finally through L1 and back to the source. During this time the indcutors L1 and L3 are charged. When the switches turn off, the energy stored inside the inductors will be released in form of a current which will go through diode D2, the load, the body diode of the switch SW1 and L1 back to the source. Similar operation happens for the switches SW3 and SW4 but with a 180° phase delay. Figure 2.14: Negative cycle operation for Bridgeless Interleaved Boost PFC The operation of the Bridgeless Interleaved Boost PFC will also depend on the duty cycle and the operation of the converter will be different for duty cycles which are greater than 0.5 compared to the duty cycles that are lower than 0.5. In the text below a detailed description will be given of the converters operations for duty cycles, D > 0.5 and D < 0.5 for the positive half cycle but the operation for the negative half cycle will be similar to the one presented below. Converter Operation for Positive Half Cycle and Duty Cycle, D > 0.5 The steady state wave forms for duty cycles > 0.5 of the converter are shown in figure 2.15 a), these wave forms are obtained from [5]. The operation of the con- verter during these conditions can be divided into four different intervals, these will be explained in the text below. Interval 1, t1-t2: At time t1, the switches SW1 and SW2 will be on, while switches SW3 and SW4 will be off. In this interval the current going through L1 and L3 will increase linearly and charge the inductors. At the same time the current going through the inductors L2 and L4 will decrease linearly and energy stored inside the inductors will be transferred to the load. Interval 2, t2-t3: At time t2 the switches SW3 and SW4 will be turned on while the switches SW1 and SW2 will remain on. The current flowing through all four inductors will increase linearly and all four inductors will be charged. Interval 3, t3-t4: 18 2. Theoretical Background At time t3 the switches SW3 and SW4 will remain on while switches SW1 and SW2 will be turned off. During this interval the current through inductors L2 and L4 will increase linearly, which will charge the inductors. The energy stored inside the inductors L1 and L3 will be released to the load through diode D1, output capaci- tance Co and body diode of switch SW2. During this interval the current through L1 and L3 will decrease linearly. Interval 4, t4-t5: During this interval all four switches will be on and the cur- rent through all four inductors will increase linearly which will charge the inductors. Operation inside the interval t5-t6 will be the same as in interval 1. Converter Operation for Positive Half Cycle and Duty Cycle, D < 0.5 The steady state wave forms for duty cycles < 0.5 of the converter are shown in fig- ure 2.15 b). The operation of the converter during these conditions can be divided into four different intervals, these will be explained in the text below. Interval 1, t1-t2: During this interval all four switches will be off. The energy stored inside the in- ductors will be released to the load through D1, D3, output capacitance and body diodes of switches SW2 and SW4. The current flowing thorough all four inductances will decrease linearly during this interval. Interval 2, t2-t3: At time t2 the switches SW1 and SW2 will turn on, while SW3 and SW4 remain off. During this interval the current flowing through inductances L1 and L3 will increase linearly which will charge up the inductors. Inductors L2 and L4 will con- tinue transferring the stored energy to the load which will result in a linear decrease of the current flowing through these inductors. Interval 3, t3-t4: During this interval all four switches will be off. All four inductors will release the stored energy to the load, which will result in a linear decrease in the current flowing through the inductors. Interval 4, t4-t5: At time t4 switches SW3 and SW4 will be turned on while SW1 and SW2 remain off. The current through L2 and L4 will increase linearly and charge the inductors. Energy stored in L1 and L3 will be transferred to the load. Due to this the current flowing through these inductors will decrease linearly. The operation inside the in- terval t5-t6 will be similar to the interval 1. The detailed converter operation during the negative half cycle will not be given here since it is similar to the positive half cycle operation. 19 2. Theoretical Background Figure 2.15: Steady state wave forms for the positive half cycle and both when duty cycle is greater than 0.5 in a) and smaller than 0.5 in b). Wave forms are obtained from [5] Design Challenges Reverse Recovery The Bridgeless Interleaved Boost PFC encounters the same issues as the Semi- Bridgeless Boost PFC when it comes to the reverse recovery of the boost diodes. Due to the fact that the converter will operate in CCM, this will lead to significant reverse-recovery losses of the diodes. Same as in the case of the Semi-Bridgeless PFC, silicon carbide diodes with no reverse-recovery charge can be used to over- come this issue. Increased Complexity Another challenge with this topology is that due the increased number of compo- nents the complexity of the drive and control circuits will increase. Due to the fact that the MOSFETs will operate in pairs with each pair being 180 degrees phase shifted from each other, sophisticated control algorithms might be required to make sure that the phase shift between gate signals of the MOSFET pairs is exactly 180 degrees. 2.3.3 Totem-Pole Bridgeless Boost PFC Utilizing GaN Tran- sistors Bridgeless Totem-Pole PFC aims to, in a similar manner as the other two bridgeless PFC topologies, improve the efficiency and power density of the PFC by reduc- 20 2. Theoretical Background ing the number of semiconducting devices in the path of the current. The circuit schematic of this topology can be seen in figure 2.16. The topology is similar to the Semi-Bridgeless PFC topology but instead of having two switching legs with one transistor on each leg, both transistors are placed on the same switching leg. This topology has been proposed in the past for other applications but its use has been limited. The reason for this is the reverse recovery issues of the Silicon (Si) MOSFETS body diodes in the totem-pole configuration. Due to the poor reverse recovery performance of the Si MOSFETS this topology was limited to the DCM or CrCM mode of operation which are not suitable for high power applications [11], [12]. In recent years with the rise of wide band gap semiconductor technologies such as Gallium Nitride (GaN) transistors, this topology has been more attractive for high power applications. The reason for this is that the GaN transistors unlike the Si MOSFETS does not have the intrinsic body diode. Due to this the reverse recov- ery issue caused by the body diode is eliminated. The diodes D1 and D2 can be slow recovery diodes, meaning a lower lower price. To further increase the efficiency of this topology, the diodes can be changed out with slow switching MOSFET transis- tors. Due to the fact that the output is never floating with respect to the input, the input voltage measurement is relatively easy to implement where a simple voltage divider can be used [11]. Also due to the non-floating output voltage, this topology has a good EMI performance. This circuit has the advantage of high efficiency, low device count and high device utilization. A more detailed converter operation is given in the text below. Figure 2.16: Schematic of the bridgeless totem pole boost PFC 2.3.3.1 Converter Operation for Positive Half Cycle Totem-Pole PFC has two different states of operation. The first state is when M2 is conducting and M1 isn’t meaning the input and the inductor is supplying the load and charging the capacitor. The current flows from the inductor and input through 21 2. Theoretical Background the capacitor and load through the diode D1 and back to the input. The other state is whenM2 isn’t conducting butM1 is, meaning the inductor is charged by the input and the capacitor is discharging through the load to keep the voltage level constant. The current flows through inductor, through M2 and then flows back to the input by D1. This can be seen in figure 2.17. Figure 2.17: Positive cycle operation of the bridgeless totem pole boost PFC 2.3.3.2 Converter Operation for Negative Half Cycle The negative half cycle also consists of two states of operation. The first one being when M2 isn’t conducting but M1 is hence the inductor and input supplies the load and capacitor. The current flows through D2 by the capacitor and load and back to the input through the switch M1. The other state being when M2 conducts and M1 isn’t, the inductor is charged whilst the capacitor keeps the voltage at the output constant. The current flows through the diode D2 first and then through M1 to charge the inductor as can be seen in figure 2.18 Figure 2.18: Negative cycle operation of the bridgeless totem pole boost PFC 22 2. Theoretical Background Design challenges Stringent Gate Driver Requirements The challenge with the GaN transistors when compared to the Si MOSFETs is that the gate driver requirements are more stringent in terms of the gate-to-source (VGS) voltage range. While the maximum allowed VGS for Si MOSFETs might be as high as +30V, the GaN devices have much lower allowed VGS which is generally closer to +6V [13]. To fully turn on the GaN transistors the VGS of generally +5V needs to be applied. This gives a quite narrow VGS range for the the GaN transistors and a accurate gate driver is needed to drive the transistors. High Side Transistor Driving Due to the Totem-pole configuration, a so called high-side driving of the transistor is required. The voltage at the source terminal of the high-side transistor will be varying and this will make the driving of the transistor more complected. The tran- sistor is turned on when a certain voltage difference occurs between the gate and source terminals of the transistors. The source terminal of the high-side transistor is connected to the input voltage which means that the voltage at source terminal can approximately reach the peak of the input voltage. This means that to turn the transistor on, a higher voltage is needed on the gate of the transistor which is non-practical. This problem can be solved with isolated gate driver or so called bootstrap configuration for the high-side switch but both of these methods will in- troduce more complexity and higher cost to the circuit. Another issue which occurs due to the Totem-pole configuration is that a so called dead time needs to be introduced in the gate signals of the transistors. Dead time is a short time where none of the transistors are conducting and is introduced in order to prevent the high shoot-through current that can occur if both of the switches are on at the same time. The length of the dead time will have an impact on the performance of the converter and should be as low as possible. 2.4 Analytical Modeling Analytical modeling is an important part of converter design. Values and equations derived in analytical modeling are used to determine proper component selection for the converter. These values are also very helpful when simulations of the converter are performed and can be used to determine if the simulation results are realistic. This chapter will present analytical modeling of the Semi-Bridgeless Boost PFC, Bridgeless Interleaved Boost PFC as well as the Bridgeless Totem-pole PFC. The equations derived in this chapter follow the method described in [14] and [15]. The following assumptions are made in order to derive the equations below: 1. The PFC is operating in CCM operation 2. Power Factor is assumed to be equal to unity 3. The output voltage of the PFC is DC without voltage ripple 23 2. Theoretical Background 2.4.1 Semi-Bridgeless PFC and Bridgeless Totem-pole PFC MOSFET RMS Current If the switching frequency is much higher than the input AC line frequency the RMS current through the transistor can be approximated as a double integral. The instantaneous transistor current is first squared and integrated to find the average value over a switching period and thereafter it is integrated once more to find the average value over the AC line period. Finally a square root of the whole expression is done to obtain the transistor RMS current. ISW−RMS = √√√√√ 1 Tac Tac∫ 0 1 Ts t+Ts∫ t i2SW (τ) dτdt (2.4) The duty cycle of the boost converter is given as D(t) = 1− Vin−peak|sin(wt)| Vo (2.5) In the case of the boost converter the current flowing through the transistor iSW (t) is equal to the input current when the transistor is on and is zero when the transistor is off. Therefore the average of transistor current squared (i2SW ) over a single switching period will be [i2SW ]Ts = 1 Ts t+Ts∫ t i2SW (t) dt = D(t) · i2in(t) = (Iin−peak · sin(wt))2 · (1− Vin−peak|sin(wt)| Vo ) (2.6) By instering (2.6) into (2.4) the following expression is obtained ISW−RMS = √√√√√ 1 Tac Tac∫ 0 I2 in−peak(1− Vin−peak|sin(wt)| Vo ) · sin2(wt)dt (2.7) The equation above can be simplified to ISW−RMS = √√√√√√ 2 Tac I2 in−peak Tac 2∫ 0 (sin2(wt)− Vin−peak·sin3(wt) Vo )dt (2.8) 24 2. Theoretical Background Finally by solving the integral term, the transistors RMS current can be obtained as in the expression below ISW−RMS = √√√√√ 1 π I2 in−peak π∫ 0 (sin2(wt)− Vin−peak·sin3(wt) Vo )dt = Iin−peak √ 1 2 − 4Vin−peak 3πVo = Pin Vin−RMS √ 1− 8Vin−peak 3πVo −→ Pin = Po η , where η = Efficiency of converter (2.9) Boost Diode Current The RMS current for the boost diode can be obtained with similar methodology used for the transistor RMS current calculation. Assuming efficiency, η = 100%, the duty cycle of the boost diode is expressed as Ddiode(t) = 1−D(t) = Vin−peak · |sin(wt)| Vo (2.10) In the same manner as the transistor current, the average of the squared diode current i2D(t) can be expressed as [i2D] = i2in(t) ·Ddiode(t) = (Iin−peak · sin(wt))2 · Vin−peak|sin(wt)| Vo (2.11) The boost diode RMS current is ID−RMS = √√√√√ 1 π I2 in−peak Vin−peak Vo π∫ 0 sin3(wt)d(wt) = Iin−peak √ 4Vin−peak 3πVo = Pin Vin−RMS √ 8Vin−peak 3πVo (2.12) Inductor RMS current The inductor RMS Current is defined as IL−RMS ≈ Iin−RMS = Pin Vin−RMS (2.13) Capacitor Current The output current of the filter capacitor consists of two components, a low fre- quency component ICout−LF which occurs at twice the line frequency and a high 25 2. Theoretical Background frequency component ICout−HF at the switching frequency. Expressions for the both components can be formulated as. ICout−LF = Pin√ 2Vo (2.14) ICout−HF = √√√√√Pin Vo √√√√ 16Vo 6 √ 2Vin−RMS − P 2 o P 2 in 2 − ( Pin√ 2Vo )2 (2.15) Boost Inductor Calculation The design of the boost inductor is done for the worst case scenario and that is when the input voltage is at its lowest. In this case that is 86 V RMS. The inductor design starts with first calculation of the duty cycle needed to boost the lowest input voltage of 86 V to the necessary output voltage of 405 V. This was calculated as D86V = Vout − √ 2 · Vin,min Vout = 405− √ 2 · 86 405 = 0.6997 (2.16) Thereafter the RMS input current as well as the inductor ripple current are calcu- lated, see IIn,RMS = Pout Vin,min,RMS · η = 3000 86 · 0.95 = 36.72A (2.17) ∆IL = Pout · √ 2 · 0.25 Vin,RMS · η = 3000 · √ 2 · 0.25 86 · 0.95 = 12.98A (2.18) In this case the maximum allowed inductor ripple was set to 25 % and efficiency η of the converter was assumed to be 95 %. Finally the inductance for both of the inductors can be calculated as L1 = L2 = Vin,min · √ 2 ·D86V ∆IL · fsw = 86 · √ 2 · 0.6997 12.98 · 100000 = 65.6µH (2.19) The switching frequency of the converter is 100 kHz. Output Capacitor Calculation As written in [16], there are three main factors to dimensioning the output ca- pacitors, the voltage ripple, the hold up time and the current going through the capacitor. These three factors are described in the following three equations where a resistive load is assumed. Vripple(p−p) = Pout 2 · π · fline · Cout · Vout (2.20) ICout(rms) = √√√√ 32 · √ 2 · P 2 out 9 · π · VacLL · Vout · η2 − (Pout Vout )2 (2.21) 26 2. Theoretical Background thold−up = Cout · (V 2 out − V 2 min) 2 · Pout (2.22) The hold up time and the allowed voltage ripple are often given depending on the load and specific use which means that (2.20) and (2.22) can be re-written to give the wanted capacitor value. The new equations become Cout = Pout 2 · π · fline · Vripple(p−p) · Vout (2.23) Cout = thold−up · 2 · Pout (V 2 out − V 2 min) (2.24) By solving these two equations one obtains two different values for the capacitance where the highest value is chosen. The output voltage ripple is set to 10V, the hold-up time is 20 ms and the minimum voltage at the PFC output is set to 370 V. With these values the output capacitance of the PFC is calculated to be 4.4 mF. 2.4.2 Bridgeless Interleaved Boost PFC The equations for the Bridgeless Interleaved Boost PFC are derived in the same manner as the Semi-Bridgeless PFC. One thing to note is that due to the interleaving the Bridgeless Interleaved PFC is dimensioned for half of the output power rating and not for full power as the Semi-Bridgeless PFC. MOSFET RMS Current The transistor RMS current is calculated as. ISW−RMS = √√√√√ 1 Tac Tac∫ 0 1 Ts t+Ts∫ t i2SW (τ) dτdt = Pin 2Vin−RMS √ 1− 8Vin−peak 3πVo (2.25) Boost Diode RMS Current The RMS current flowing through the boost diode will be ID−RMS = √√√√√ 1 π I2 in−peak Vin−peak Vo π∫ 0 sin3(wt)dt = Pin 2Vin−RMS √ 8Vin−peak 3πVo (2.26) InDuctor RMS Current The inductor RMS current flowing through each inductor will be IL−RMS ≈ Iin−RMS 2 = Pin 2Vin−RMS (2.27) 27 2. Theoretical Background Capacitor Current The low and high frequency components of the output capacitor current are given as. ICout−LF = √ 2Po 2Vo (2.28) ICout−HF = Pin Vo √√√√ 16Vo 6πVin−peak − P 2 o P 2 in (2.29) Boost Inductor Calculation The inductor value is calculated as. L = Vout 4 · fsw ·∆I (2.30) The peak-peak current ripple ∆I is 0.4Iin,RMS. Due to the ripple cancellation phe- nomenon in the Bridgeless Interleaved PFC the current ripple is allowed to be higher when compared to the Semi Bridgeless and Totem-pole PFC. The output capaci- tance is calculated in the same manner as for the Semi-Bridgeless PFC. 2.5 Small Signal Models of Bridgeless PFC Topolo- gies Small signal models represent a linearized system. The large signal model is evalu- ated at a steady state operating point and consider the dynamics for a small signal perturbation 2.5.1 Semi Bridgeless and Bridgeless Totem-pole Boost PFC The small signal model for the Semi-Bridgeless and the Totem-Pole topology will be exactly the same which means that the derivations will also be identical. In this section the Semi-Bridgeless small signal model will be derived. First and foremost the averaged large signal model needs to be derived to get necessary parameters to derive the small signal model. This is done by inserting the averaged current and voltage from the four states described in converter operation for positive and negative half cycle. As described in sections 2.5.1, 2.5.2 and 2.5.3, in the first two states the input voltage is positive and for the other two negative. The first state being when M1 is conducting and the inductor L1 is charging. diin dt = vin L1 dvC1 dt = − vC1 C1R1 (2.31) Second state is when the M1 isn’t conducting and L1 is supplying the capacitor and the load. 28 2. Theoretical Background diin dt = vin − vC1 L1 dvC1 dt = iC1 + iR1 C1 − vC1 C1R1 (2.32) The third state is when M2 is conducting and inductor L2 is charging, diin dt = vin L2 dvC1 dt = − vC1 C1R1 (2.33) The fourth and final state is when M2 isn’t conducting and L2 is supplying the capacitor and the load, diin dt = vin − vC1 L2 dvC1 dt = iC1 + iR1 C1 − vC1 C1R1 (2.34) With the values of the voltage over the capacitor and the input current from (2.31) through (2.34) the large signal model can be built. Since the inductors L1 and L2 are asumed to have the same value the large signal model can be simplified to two matrix systems representing when the switches are on and when the switches are off. The both inductors are identical and thereby, L1 = L2 = L. So for the case when both switches are on i.e state one and three the matrix equation given below is obtained. [ diin dt dvC 1 dt ] = [ 0 0 0 − 1 C1R1 ] · [ iin vC1 ] + [ 1 L 0 ] · vin (2.35) The two matrices in 2.35 have representing parameters A1 and B1 respectively. The other matrix equation representing state two and four which represents when both switches are off is presented below in 2.36. [ diin dt dvC 1 dt ] = [ 0 − 1 L 1 C1 − 1 C1R1 ] · [ iin vC1 ] + [ 1 L 0 ] · vin (2.36) The two matrices in eq 2.36 have representing parameters A2 and B2 respectively. The duty cycle needs to be accounted for and is done with duty cycle = D,D′ = 1 − D. For state space averaging (2.35) is multiplied with D and (2.36) with D’. Both parts are combined to obtain matrix equations for all states which then can be simplified to a combined A and B matrices seen in (2.37) respectively. ẋ = (A1x+B1vin)D + (A2x+B2vin)D′ → ẋ = (A1D + A2D ′)x+ (B1D +B2D ′)vin (2.37) To transform this new matrix system into the small signal model the duty cycle, Vin, VC0 and iin need to be transformed. This is done by letting them be represented with a DC part plus a small signal ac part seen in equation 2.38. 29 2. Theoretical Background D = Davg + d̂ vin = Vin−avg + v̂in x = Xavg + x̂ (2.38) The new values needs to be substituted in to equation 2.39, to get a non linear small signal model which can be seen in (2.39). To linearize this some assumptions need to be made, namely that products of two perturbation variables are neglectable compared to the rest and therefore considered equal to zero. This will give us the following eq 2.40. ẋ = (A1(Davg + d̂) + A2(1− (Davg + d̂))) · (Xavg + x̂) +(B1(Davg + d̂) +B2(1− (Davg + d̂))) · (Vin−avg + v̂in) (2.39) ˙̂x = AXavg +BVin−avg +Ax̂+Bv̂in + ((A1−A2)Xavg + (B1−B2)Vin−avg)d̂ (2.40) To get the steady state model, this equation is evaluated with all the time derivatives in (2.40) being set to zero. The matrix A need to be inverted and this is done to solve for the matrix Xavg seen below. dxavG dt = AXavg +BVin−avg = 0 xavG = −A−1BVin−avg (2.41) → XavG = [ Iin−avg VC1−avg ] =  Vin−avg R0(1−D)2 Vin−avg 1−D  (2.42) With this we can get the final and linearized model by incorporating 2.41 in 2.40. This gives us the small signal linearized state space model seen in equation 2.43. dx̂ dt = Ax̂+Bv̂in + ((A1 − A2)Xavg + (B1 −B2)Vin−avg)d̂ (2.43) d dt [ ˆiin ˆvC1 ] = [ 0 − (1−D) L 1−D C1 − 1 C1R1 ] · [ ˆiin ˆvC1 ] + [ 1 L 0 ] · v̂in +  Vin−avg L(1−D) − Vin−avg C1R1(1−D)2  · d̂ (2.44) The model can then be converted into s-domain to get the transfer funcitons, seen below. ((A1 − A2)Xavg + (B1 −B2)Vin−avg)d̂ = Ed̂ With v̂in = 0 → x̂(s) d̂(s) = (s1− A)−1E With d̂ = 0 → x̂(s) v̂in(s) = (s1− A)−1B (2.45) 30 2. Theoretical Background x̂(s) d̂(s) = [ ˆiin(s) ˆvC1(s) ] d̂(s) = 1 s2 + s C1R1 + (1−D)2 C1L (s+ 1 C1R1 )(Vin−avg L(1−D) ) + Vin−avg(1−D) C1R1L(1−D)2 Vin−avg C1L − Vin−avgs C1R1(1−D)2  (2.46) with v̂in(s) = 0 → ˆiin(s) d̂(s) = vin−avg(2 + C1R1s) R1(1−D)3( C1Ls2 (1−D)2 + Ls R1(1−D)2 + 1) (2.47) The transfer function for the output voltage depending on the input current can be seen below. ˆvC1(s) ˆiin(s) = vin−avg ·R1 2 · vC1(R1C1s+ 1) (2.48) 2.5.2 Bridgeless Interleaved Boost PFC For the Bridgeless Interleaved Boost PFC, the methodology for finding the small signal model and transfer function is the same as for the Semi-Bridgeless PFC. The exception being how the system is analysed, the interleaved topology has four switches and two controllers. To fit the transfer function for use in one of these controllers the topology is effectively halved to be only two switches/legs where only one of the inductor currents is of interest. Firstly analyzing the different modes of operation and drawing the same conclusions as for semi bridgeless and totem pole PFC. diL1 dt = Vin 2 · L dVC0 dt = iL2 C0 − VC0 Rload · C0 (2.49) diL1 dt = Vin − VC0 2 · L dVC0 dt = iL1 C0 − VC0 Rload · C0 (2.50) Since the system is symmetrical over positive and negative half cycles, only one of them needs to be considered. Here, the positive half cycle is chosen, as seen in the above equations. This gives the following matrix equations. A1 = [ 0 0 0 −1 Rload·C0 ] , X = [ iL1 VC0 ] , A2 = [ 0 −1 2·L 1 C0 −1 Rload·C0 ] , B1 = B2 = [ 1 2·L 0 ] (2.51) A = (A1 ·D + A2 · (1−D)) = [ 0 − (1−D) 2·L 1−D C0 −1 Rload·C0 ] (2.52) B = (B1 ·D +B2 · (1−D)) = [ 1 2·L 0 ] (2.53) introducing the same perturbations as in the earlier section using (2.38) through (2.40) and solving for Xavg we get the following equation. Xavg = −A−1BVin−avg = − [ 0 − (1−D) 2·L (1−D) C0 −1 Rload·C0 ]−1 [ 1 2·L 0 ] Vin−avg =  Vin−avg Rload·(1−D)2 −Vin−avg D−1  (2.54) 31 2. Theoretical Background Translating this to s-domain results in the transfer function for the current iL1(s) d̂(s) by doing the same operations as equations (2.43) through (2.47), as seen in the equations below. diL1(s) d̂(s) dvC 0(s) d̂(s)  = [ s 1−D 2·L D−1 C0 s+ 1 Rload·C0 ]−1 ( [ 0 1 2·L −1 C0 0 ]  Vin−avg Rload·(1−D)2 −Vin−avg D−1 ) (2.55) with v̂in(s) = 0 → iL1(s) d̂(s) = −2Vin−avg − C0RloadVin−avgs Rload(D − 1)3 + 2C0LRloads2(D − 1) + Ls(D − 1) (2.56) The transfer function for the output voltage depending on the input current can be seen below. ˆvC0(s) ˆiin(s) = vin−avg 2vC0C0s (2.57) 32 3 Simulations 3.1 Modeling of Topologies The chosen topologies were first modeled in continuous time utilizing ideal compo- nents directly based on the theoretical values calculated in chapter 2. The circuits were then tested with a rudimentary control system which creates a constant duty cycle to the switches to ensure the functionality of the PFC topologies. In order to reduce the simulation time, the models were converted from continuous time domain to discrete time domain. The rudimentary control systems were then replaced with digital PI current controllers in an open loop configuration to test the power factor correction capability of the systems. Once it was ensured that the current controller were working as expected and were able to place the input current in phase with the input voltage, the systems were reconfigured to closed loop where another PI controller was introduced which controls the output voltage. The input and output signals were then observed to ensure the correct functionality of the whole system. The modeling of each topologies will be discussed in more detail in the sections below. 3.1.1 Semi-Bridgeless Boost PFC The Simulink circuit model of the Semi-Bridgeless Boost PFC can be seen in figure 3.1. Modeling of this circuit is done using MOSFETs and diodes with ideal switching. This means that the switching behavior is assumed to be perfect and that the devices will behave as linear resistors with constant on resistance when they are conducting. This means that the switching losses are not included in the simulations, which is a simplification. In reality the switching losses can account for a significant portion of the total power losses [17]. Especially at high frequency and/or at light loads the switching losses can trump the conduction losses of the device [17]. The reason ideal switching devices are used is because the simulations were simplified at the beginning stage and due to the time constraints it was not possible to replace the components to more realistic ones at the later stage. Components and component values used for the simulations can be found in table 3.1. The values for the capacitance and inductance are calculated in chapter 2.4.1. It should be noted that the inductance value calculated is approximately five times lower than the actual value used in the simulations. The reason for this is that with the calculated value, the total harmonic distortion was deemed to be too high at the higher input voltages. The same inductance is also used for the Totem Pole PFC. 33 3. Simulations Table 3.1: Component values used for the simulation of Semi-Bridgeless Boost PFC Switching Frequency 100 kHz Sampling Frequency 3 MHz Boost Inductors L1,L2 L = 300 µH, R = 80.7mΩ Output Capacitor 4.4 mF Boost Diodes SCS320AJ Mosfets NTP082N65S3F Return Diodes DSEI120-06A Figure 3.1: Model of the Semi-Bridgeless Boost PFC in Simulink 3.1.2 Bridgeless Interleaved Boost PFC The modeling of the Bridgeless Interleaved Boost PFC was done in the same manner as the Semi-Bridgeless PFC, ideal switching MOSFETs and diodes were used. The component values used can be seen in table 3.2 and the Simulink model can be seen in figure 3.2. Table 3.2: Component values used for the simulation of Bridgeless Interleaved PFC Switching Frequency 100 kHz Sampling Frequency 10 MHz Boost Inductors L1,L2,L3,L4 L = 130 µH, R = 52 mΩ Output Capacitor 4.4 mF Boost Diodes SCS320AJ Mosfets NTP082N65S3F Return Diodes DSEI120-06A 34 3. Simulations Figure 3.2: Model of the Bridgeless Interleaved Boost PFC in Simulink 3.1.3 Bridgeless Totem-Pole Boost PFC utilizing GaN Tran- sistors The Simulink circuit model of the Totem-pole PFC can be seen in figure 3.3. Due to the fact that the there is no add-in model for GaN transistors in any of the available Simulink libraries a simplification is made where the MOSFETS with ideal switching are used instead in the same as in the other two topologies. The difference in this case is that the intrinsic body diode is removed from the device model. The component values used for modeling can be found in 3.3. Table 3.3: Component values used for the simulation of Bridgeless Totem-Pole Boost PFC utilizing GaN transistors Switching Frequency 100 kHz Sampling Frequency 3 MHz Boost Inductor L L = 300 µH, R = 80.7mΩ Output Capacitor 4.4 mF Transistors GS66516T Slow Diodes DSEI120-06A 35 3. Simulations Figure 3.3: Model of the Totem-pole Boost PFC in Simulink 3.2 Implementation of the Control Systems The control systems for the different topologies were built in the same manner, with a slower outer voltage controller and a fast inner current controller. The block diagram of the controller structure can be seen in figure 3.4. First, a voltage reference is given which is compared to the output voltage and the error is sent to the voltage PI controller. The output of the voltage controller is then multiplied with the the absolute value of the input voltage. The product of the input voltage and the output from the voltage controller will be the current reference which is sent to the inner current control loop. The current reference is compared with the inductor current and the error is sent to the current PI controller. The output of the current controller will be the duty cycle which will be sent to the modulator that will create the PWM which will drive the switches. Figure 3.4: Block diagram of the controller structure 36 3. Simulations 3.2.1 Tuning of the Controllers To achieve the desired performance of the PFC it is important that the inner current controller is fast enough to track the input voltage and that outer voltage controller is able to bring up the output voltage to reference in reasonable amount of time without negatively affecting the current controller. To tune the controller is was first necessary to derive the current and voltage transfer functions for the chosen topologies, the derived transfer functions can be seen in sections 2.5.1 and 2.5.2. Thereafter the controller was tuned with help of the bode plots for the transfer functions using Sisotool in Matlab. The controller performance is defined by the cross-over frequency fc and the phase margin θpm. The cross-over frequency is the frequency where the magnitude curve crosses the zero dB axis in the bode plot and the phase margin is defined as the difference between the phase of the response and the -180 degrees line of the bode plot at cross-over frequency. The cross-over fre- quency determines the speed and the phase margin will determine the stability of the response. The cross-over frequency will affect the total harmonic distortion of the PFC and should be as high as possible in order to give good THD performance [18]. There is a limitation to how high the cross-over frequency of the current open loop response can be, a rule of thumb is that it should be somewhere in between 10- 20 % of the switching frequency [18]. In this work, the chosen cross-over frequency of the current open loop response for all three topologies is chosen to be close to 10 % of the switching frequency which is 10 kHz. The phase margin will affect the overshoot of the response. A rule of thumb is that the phase margin of the current controller should be between 45-60 degrees [18]. The current controllers for all three topologies are tuned so that the current open loop response has close to 60 degrees of phase margin. The current controller for all three topologies were tuned at the midpoint of the required AC input voltage range for the PFC topologies, which is 175 V RMS see table 1.1. This is so that the current controller can have a good behavior for the whole range of the required input voltages. Also the controllers were tuned at full load of 3kW in order to guarantee the best THD performance at full load operation. The requirements for the voltage controller is to attenuate the output voltage ripple which occurs at twice the line frequency and to have close to 90 degrees of phase mar- gin because the voltage overshoot at the output is not desired [18]. The cross-over frequency of the voltage controller should be low enough to attenuate the output voltage ripple and also low enough to not affect the reference tracking of the current controller. The cross-over frequency of the voltage controller should be set to 10-20 % of 2 · fline [18]. In this work the voltage controllers are tuned so that the voltage open loop response has a cross-over frequency of fc ≤ 20 Hz at 230V RMS input voltage and close to 90 degrees of phase margin. As for the current controller the voltage controller is tuned for full load operation, but unlike the current controller, the voltage controller is tuned for higher input voltage. In this way the voltage controller is not unacceptably slow at low input voltages. The bode plots used for current and voltage controller tuning for the Semi-Bridgeless Boost PFC can be seen in figures 3.5 and 3.6 respectively. The tuning is done in the same manner for the other two topologies. In the subsections below a more detailed description of the 37 3. Simulations Simulink controller implementation for the different topologies will be given. Figure 3.5: Bode plot for the current open loop response with and without the current controller for the Semi-Bridgeless PFC 38 3. Simulations Figure 3.6: Bode plot for the voltage open loop response with and without the voltage controller the Semi-Bridgeless PFC 3.2.2 Simulink Implementation and System Testing Controller Simulink models for each topology as well as the testing of closed loop systems are presented in this section. 3.2.2.1 Semi-Bridgeless Boost PFC The closed loop controller implemented in Simulink follows the structure from figure 3.4. The closed loop controller implemented in Simulink can be seen in figure 3.7. The input voltage, output voltage and the sum of the current flowing through the switches and the current flowing to the load and the capacitor are first measured and normalized. The output voltage is compared to the reference and the error is then sent to the voltage controller. The input voltage is rectified and multiplied with the output of the voltage controller. The product is then compared to the measured current and error is sent to the current control loop which generates the PWM signal necessary for driving the switches. 39 3. Simulations Figure 3.7: Simulink model of the closed loop controller for the Semi-Bridgeless Boost PFC Once the controller was implemented, the testing of the whole system was done for different input voltages. The input current, input voltage and load voltage waveforms for input voltage of 230V RMS and load of 3kW can be seen in figures 3.8 and 3.9 respectively. In figure 3.8 the input voltage amplitude is scaled in order to easier compare the current and voltage waveforms. From this figure, it can be seen that the input current is tracking the input voltage, which indicates that the current controller is working as desired. During the simulations it was observed that the input current has a very high value during the first half cycle of operation, this is due to the inrush current. From figure 3.9 it can be seen that the load voltage follows reference which is 405V. It can be seen that the voltage rises quickly to just below 400 V and drops just before it once again rises and continues to reference. The fast initial rise in voltage is due to the large in-rush current. Once the current passes the inrush stage, the voltage will drop for a short moment. This is because the voltage controller is quite slow and it will take some time for it to regulate the voltage back to the setpoint. It can be seen that the steady state for the load voltage is reached just before approximately 1.5 seconds. In reality the voltage controller should be faster but for this work, this time was deemed to be acceptable. The voltage controller can be tuned for a faster response but there is a limit for how fast it can be before it starts to affect the voltage tracking capability of the current controller. 40 3. Simulations Figure 3.8: Steady state waveform of the input current in red and source voltage in blue for Semi-Bridgeless Boost PFC Figure 3.9: Load voltage waveform for Semi-Bridgeless Boost PFC 3.2.2.2 Bridgeless Interleaved Boost PFC The control system for the Bridgeless Interleaved Boost PFC is structured in the same way as for the Semi-Bridgeless PFC. The difference in this case is that two current PI controller are used instead of one, with each of them getting half of the respective current references. For this topology the switches are driven in pairs and the PWM signals for these pairs are phase shifted with 180 degrees. The complete control circuit can be seen in the figure 3.10. 41 3. Simulations Figure 3.10: Simulink model of the closed loop controller for the Bridgeless Inter- leaved Boost PFC The system response for the input voltage of 230V RMS and load of 3kW is presented in in figures 3.11 and 3.12. The load voltage reaches steady state after approximately 1 second. Figure 3.11: Steady state waveform of the input current in red and source voltage in blue for Bridgeless Interleaved Boost PFC 42 3. Simulations Figure 3.12: Load voltage waveform for Bridgeless Interleaved Boost PFC 3.2.2.3 Bridgeless Totem-Pole Boost PFC Utilizing GaN transistors The control system for the Bridgeless Totem-Pole PFC is structured in the same way as for the other two topologies. The major differences of this controller compared to the other two topologies is that the PWM signals are inverted compared to each other and a polarity detection is introduced. The controller will sense the polarity of the input voltage and adjust which of the two PWM signals is sent to which switch depending on if the input voltage is in the positive or negative half cycle. Figure 3.13: Simulink model of the closed loop controller for the Totem-pole Boost PFC utilizing GaN transistors As for the other two topologies, the system response for the input voltage of 230V RMS and load of 3kW is presented in in figures 3.14 and 3.15. It can be seen that 43 3. Simulations the current tracks the input voltage as desired and that the steady state for the load voltage is reached just before approximately 1 second. Figure 3.14: Steady state waveform of the input current in red and source voltage in blue for Totem-pole Boost PFC utilizing GaN transistors Figure 3.15: Load voltage waveform for Totem-pole Boost PFC utilizing GaN tran- sistors 44 4 Results In this section the simulation results as well as some of the results from the literature study will be presented. 4.1 Efficiency 4.1.1 AC Input Voltages Efficiency plots for six different input voltages can be seen in figures 4.1-4.3. It can be seen that the Bridgeless Interleaved Boost PFC topology is the most efficient of the three topologies for the majority of input voltages and load powers. An exception to this is seen at the low load powers and high input voltages. The Totem-Pole PFC is just below the Bridgeless Interleaved PFC at most of the input and load ranges but has higher efficiency at low load operation at the input voltage of 240 and 264V RMS. It can be seen that the Semi Bridgeless PFC is the least efficient out of the three. This is most likely a result of the conduction losses being the biggest contributor to efficiency drop in the simulations. The Bridgeless Interleaved PFC is the most efficient since the current going through each of the active components is effectively halved compared to the input current. The Totem- Pole PFC is not quite as efficient as the Bridgeless Interleaved but performs better than the Semi-Bridgeless PFC. This is because the transistors in the circuit have lower resistance and there are also less components in the current path. The peak efficiency for Bridgeless Interleaved PFC, Semi-Bridgeless PFC and Totem-pole PFC was estimated to be 97.86%, 96.93% and 97.55% respectively, with a input voltage of 264V RMS and a output of 3000W. Similar, but just a bit lower efficiencies can be observed at a voltage of 230V RMS. 45 4. Results Figure 4.1: Efficiency plots for 86V, 50Hz input voltage and 120V, 60Hz input voltage for the chosen topologies Figure 4.2: Efficiency plots for 175V and 230V, 50Hz input voltages for the chosen topologies 46 4. Results Figure 4.3: Efficiency plots for 240V and 264V, 50Hz input voltages for the chosen topologies 4.1.2 DC Input Voltages Efficiency results for 350V and 400V DC input voltages are presented in the figure 4.4. From the figure it can be seen that the Totem-Pole PFC topology is the most efficient of the three, for a load power lower than 2.5 kW for 350V input and load power lower than 2 kW for 400V input. The Bridgeless Interleaved PFC is the most efficient at full load of 3 kW, while the Semi-Bridgeless PFC has the lowest efficiency out of the three. The peak efficiency of 99.27 % for Totem-Pole PFC is observed at the load power of 1.5 kW and a input voltage of 400V. The peak efficiency for Bridgeless Interleaved and Semi Bridgeless PFC were 99.25 % at load of 3 kW and 98.75 % at load of 1.5 kW, respectively. It can be seen that unlike for the AC inputs, the efficiency curves of all three topolo- gies are more linear even for lower power. In the AC case, the low efficiency for low loads can be attributed to the high amount of harmonic distortions in the current. The current controller is tuned for 3 kW operation and behaves poorly at low loads. This is not the case for the DC input voltages. The current distortions for DC volt- ages were not significant. This can also be the reason why the Totem-Pole PFC has a higher efficiency than Bridgeless Interleaved PFC for lower load power. For AC input voltages, the current controller might be slightly better tuned for the Bridge- less Interleaved when compared to the Totem-Pole and due to this the Bridgeless Interleaved PFC experienced lower THD which lead to a greater efficiency. Another possible reason is that due to the inherent current ripple cancellation of the Bridge- less Interleaved PFC, the THD was lower than the other topologies which again lead to a greater efficiency for this topology. 47 4. Results Figure 4.4: Efficiency plots for 350V and 400 V DC input voltages for the chosen topologies 4.2 Harmonic Distortion and Power Factor The total harmonics distortion for six input voltages and different loads can be seen in figures 4.5 - 4.7. The same trend as in the efficiency plots can be observed, the Bridgeless Interleaved PFC has the best performance for most of the input voltages and loads. The reason for this is probably a result of its inherent input current ripple cancellation. It can also be seen that the Semi-Bridgeless PFC has the highest THD out of the three topologies. One reason for why a difference in THD values can be seen between the Semi-Bridgeless PFC and the Totem-Pole PFC might be due to the small signal modeling of the topologies which is used to tune the current controller. The small signal model for both topologies is derived in the same way, but in the case of the Semi-Bridgeless PFC a simplification is made where it is assumed that all of the return current will flow through the return diodes. In reality this is not the case, and a significant portion of the return current will flow thorough the body diode of the non-switching MOSFET. The power factor for the three topologies was found to be better for higher power output regardless of input voltage. It was also found that as the input voltage in- creased, the power factor for the lowest power output got progressively worse across the board, resulting in a power factor as low as 0.90 for the three topologies. The power factor for all power levels above 500 W was above 0.98. The most likely reason for this being the case is because the controllers for all topologies were tuned for higher power levels. The low power factor at the lowest output power is as expected since the total harmonic distortion is at its highest during that power level. 48 4. Results Figure 4.5: Total harmonic distortion plots for 86V, 50Hz input voltage and and 120V, 60Hz input voltage for the chosen topologies Figure 4.6: Total harmonic distortion plots for 175V and 230V, 50Hz input voltages for the chosen topologies 49 4. Results Figure 4.7: Total harmonic distortion plots for 240V and 264V, 50Hz input voltages for the chosen topologies 4.3 Input Current Ripple The input current ripple for the three topologies was found to be constant for a spe- cific voltage input regardless of power output. For all voltage levels and all topologies the current ripple was below 5A with the highest being 3.3A. The Totem-Pole PFC and the Semi-Bridgeless PFC had very similar input current ripples whereas the Bridgeless Interleaved PFC topology was halved in comparison. This is due to the inherent current ripple cancellation mentioned before. 4.4 Inrush Current 4.4.1 AC Input Voltages From the simulations it was observed that all topologies experience significant inrush current during the first half cycle of the input voltage. The highest inrush current is experienced at the highest input voltage, since that is when the voltage difference between the input voltage and the output capacitor is the greatest. The Totem-Pole PFC having the lowest conductive resistance due to lowest amount of components and its switches, it experienced the highest inrush current of the three topologies. This occurs at 264V and the amplitude of the inrush was 592.7A for a very short period of time. The highest experienced inrush current by the Bridgeless Interleaved topology is 498.8A. In contrast to the Totem-Pole, this current is divided between two legs of the circuit lowering the current flowing through sensitive components. The Semi-Bridgeless PFC experiences the highest inrush at the same point as the other two topologies and the amplitude is roughly the same as for the Bridgeless Interleaved. One way to reduce the current flowing through sensitive semiconductors is with additional circuitry. Two so called peak charging diodes can be connected between line and neutral of the voltage source and the output capacitor. As seen 50 4. Results in the semi bridgeless PFC topology. With these diodes in place the inrush current can circumvent the sensitive semiconductors and flow straight to the capacitance. The inrush diodes, D1 and D3 can be seen in figure 2.9. 4.4.2 DC Input Voltages The inrush current for the DC input voltages was higher than for the AC input. The peak inrush currents observed were 1532A, 1400A, 871A at 400V input for the Bridgeless Interleaved, the Semi-Bridgeless PFC and Totem-Pole PFC respectively. It can be seen that the inrush current is significantly larger for the DC input voltages. This is partly due to the fact the DC input voltages are higher than the peak voltage of the AC input and partially that in the case with DC simulations, a large voltage is directly available from the source. In the case of the simulations with AC input, the source voltage will be sinusoidal which means that it will start of at zero and ramp up to peak value. The peak value is reached after one quarter of the cycle which leads to a more of a soft start when compared to instantly applying the DC input voltage. Due to the high inrush current, additional circuitry is needed to lower the inrush current to more reasonable values. 4.5 Component Count In the table below the component count as well as the component type used for each of the chosen topologies is presented. One should note that the peak charging diodes needed for the in-rush protection are excluded from this table. From the table can be seen that the topology with the lowest component count is the Totem- Pole (BTP) PFC, followed by the Semi-Bridgeless (SBL) PFC and finally by the Bridgeless Interleaved PFC (BLIL). Of course, the total amount of components is not the only thing of interest but also the type of components used. Due to the use of the GaN transistors and the higher cost of them when compared to Si Mosfets, the total cost of the Totem-Pole PFC is generally higher when compared to the Semi-Bridgeless PFC. On the other hand the amount of fast diodes and MOSFETs used in the Bridgeless Interleaved PFC topology will lead to a cost which is generally closer to the cost of the Totem-Pole PFC. Table 4.1: Table of number of specific components for specific topology BLIL SBL BTP Fast diodes 4 2 0 Slow diodes 0 2 2 Mosfets 4 2 0 Inductors 4 2 1 GaN Transistors 0 0 2 51 5 Conclusion The aim of this thesis was to investigate and compare bridgeless PFC topologies that are suitable for power levels of 3kW. It was found that the three most suitable topologies for this power level are Semi-Bridgeless Boost PFC, Bridgeless Interleaved Boost PFC and Totem-Pole Boost PFC utilizing Gallium Nitride transistors. From the simulations that were carried out it was observed that the Bridgeless Interleaved PFC had the highest efficiency for most of the input voltages and output loads. Totem-Pole PFC was closely behind the Bridgeless Interleaved PFC and finally the Semi-Bridgeless PFC had the lowest efficiency out of the three. The same trend can be seen in the total harmonic distortion, power factor and input current ripple where the Bridgeless Interleaved PFC performed better than the other two topologies. All three topologies experience significant in-rush current at the start of the operation. In the case of the Bridgeless Interleaved PFC unlike the other two topologies, this current will be divided between two of the switching legs of the converter. This means that the components experience half of the in-rush current and as a result of this, additional circuitry for in-rush handling might not be necessary. This is not the case for the other two topologies. With this said, the Bridgeless Interleaved is the topology which contains the highest amount of components out of the three, which can be correlated to a higher price for the converter compared to the other two topologies. 52 6 Discussion and Future Work As previously mentioned in chapter 3, the simulations of all three topologies were executed using ideal switching devices meaning that the switching losses of the tran- sistors and reverse recovery losses of the diodes are not included in the simulations. In reality the switching losses and reverse recovery losses can be a significant portion of the total power losses. With that said, the efficiency results obtained from the simulations match quite closely to the experimental results seen in the literature study when it comes to full load operation and the loads near the full load oper- ation [5], [8], [19], [20], [21], [12], [22]. The reason for this is probably that the converter design was more extensively optimized, which was not possible to do in this thesis due to the time constraints. One thing to note when it comes to the Totem-Pole PFC is, as mentioned in chapter 2.3.3 that the slow diodes of the the converter can be replaced with slow switching MOSFETs to further increase the ef- ficiency of PFC. With this implementation it is expected that the Totem-Pole PFC could achieve highest efficiency out of the three topologies - up to 99 % [12], [22], [23]. This project has investigated the performance of three bridgeless PFC topologies with help of a literature study as well as computer simulations. The simulations done in this project were simplified, where the ideal switching devices instead of more realistic components were used. These kind of simulations in combination with the literature study can be used to determine general performance of the PFC topologies but does not give 100 % accurate results. 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Dusmez, Designing a 99% efficient totem pole pfc with gan, 2017. 55 https://www.ti.com/tool/TIDA-01604 https://www.ti.com/tool/TIDA-01604 https://www.powerelectronics.com/technologies/gan-transistors/article/21863347/gan-basics-faqs https://www.powerelectronics.com/technologies/gan-transistors/article/21863347/gan-basics-faqs https://www.powerelectronics.com/technologies/gan-transistors/article/21863347/gan-basics-faqs https://www.ti.com/lit/ml/slyy131/slyy131.pdf https://www.onsemi.com/pub/Collateral/HBD853-D.PDF https://www.onsemi.com/pub/Collateral/HBD853-D.PDF https://www.vishay.com/docs/65677/an844.pdf https://www.vishay.com/docs/65677/an844.pdf https://www.nxp.com/docs/en/application-note/AN5257.pdf https://doi.org/10.1109/TPEL.2013.2275739 https://doi.org/10.1109/TPEL.2013.2275739 https://doi.org/10.1109/INTLEC.2011.6099764 https://doi.org/10.1109/VPPC.2010.5729187 https://www.infineon.com/dgdl/Infineon-Design_guide_Gallium_Nitride-CoolGaN_totem-pole_PFC_power_loss_modeling-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626d82c047016d95daec4a769a https://www.infineon.com/dgdl/Infineon-Design_guide_Gallium_Nitride-CoolGaN_totem-pole_PFC_power_loss_modeling-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626d82c047016d95daec4a769a https://www.infineon.com/dgdl/Infineon-Design_guide_Gallium_Nitride-CoolGaN_totem-pole_PFC_power_loss_modeling-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626d82c047016d95daec4a769a Introduction Background Aim Problem Description Scope Sustainable Aspects Theoretical Background AC/DC Converters Power Factor Correction Total Harmonic Distortion AC/DC Conversion Modes of Operation for Power Converters Continuous Conduction Mode (CCM) Discontinuous Conduction Mode (DCM) Critical Conduction Mode (CrCM) Active Power Factor Correction Topologies Active Boost PFC Interleaved Boost PFC Bridgeless Power Factor Correction Topologies Semi-Bridgeless PFC Converter Operation for Positive Half Cycle Converter Operation for Negative Half Cycle Bridgeless Interleaved Boost PFC Converter Operation for Positive Half Cycle Converter Operation for the Negative Half Cycle Totem-Pole Bridgeless Boost PFC Utilizing GaN Transistors Converter Operation for Positive Half Cycle Converter Operation for Negative Half Cycle Analytical Modeling Semi-Bridgeless PFC and Bridgeless Totem-pole PFC Bridgeless Interleaved Boost PFC Small Signal Models of Bridgeless PFC Topologies Semi Bridgeless and Bridgeless Totem-pole Boost PFC Bridgeless Interleaved Boost PFC Simulations Modeling of Topologies Semi-Bridgeless Boost PFC Bridgeless Interleaved Boost PFC Bridgeless Totem-Pole Boost PFC utilizing GaN Transistors Implementation of the Control Systems Tuning of the Controllers Simulink Implementation and System Testing Semi-Bridgeless Boost PFC Bridgeless Interleaved Boost PFC Bridgeless Totem-Pole Boost PFC Utilizing GaN transistors Results Efficiency AC Input Voltages DC Input Voltages Harmonic Distortion and Power Factor Input Current Ripple Inrush Current AC Input Voltages DC Input Voltages Component Count Conclusion Discussion and Future Work References