Design and Analysis of a Phase Shifted Full Bridge Converter for High Efficiency Operation Master’s Thesis in Electric Power Engineering Johannes Karlsson & Simon Larsson DEPARTMENT OF ELECTRICAL ENGINEERING CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2023 www.chalmers.se www.chalmers.se Master’s thesis 2023 Design and Analysis of a Phase Shifted Full Bridge Converter for High Efficiency Operation Johannes Karlsson Simon Larsson Department of Electrical Engineering Division of Electric Power Engineering Chalmers University of Technology Gothenburg, Sweden 2023 Design and Analysis of a Phase Shifted Full Bridge Converter for High Efficiency Operation Johannes Karlsson & Simon Larsson © Johannes Karlsson & Simon Larsson, 2023. Supervisor: Jacob Viktorsson, Saab AB Supervisor: Daniel Samuel, Knowpeak AB Examiner: Torbjörn Thiringer, Department of Electrical Engineering Master’s Thesis 2023 Department of Electrical Engineering Division of Electric Power Engineering Chalmers University of Technology SE-412 96 Gothenburg Telephone +46 31 772 1000 Cover: Circuit board of the DC/DC full bridge converter designed in this project. Typeset in LATEX, template by Kyriaki Antoniadou-Plytaria Gothenburg, Sweden 2023 iv Design and Analysis of a Phase Shifted Full Bridge Converter for High Efficiency Operation Johannes Karlsson & Simon Larsson Department of Electrical Engineering Chalmers University of Technology Abstract Saab investigates if there is a possibility to replace an existing DC/DC converter with an alternative converter design. Saab therefore wanted a phase shifted full bridge designed and constructed, capable of delivering 1.2 kW for an output voltage of 56 V, with a maximum output voltage ripple of 1%. The input voltage range is set to 350-400 V. The final design was then compared with an alternative solution, an LLC converter, in order to compare possible advantages with each solution. The phase shifted full bridge converter was successfully designed and implemented in simulations. A list of components and a circuit schematic to realise the design in a physical implementation was then presented and the converter was constructed. Due to oscillations and a faulty snubber design, the phase shifted full bridge converter could not reach the aspirations and the maximum output power was limited to 400 W. The voltage ripple was not within the goal of 1% and the efficiency of the LLC was higher. However, the advantages of using a phase shifted full bridge compared to a LLC was also presented where a fully operational converter was considered. Keywords: PSFB Converter, DC/DC converter, Current doubler, Transformer de- sign, Feedback control, LLC converter. v Acknowledgements We are grateful for the possibility we were given from Saab to do our Master’s thesis at one of their departments of electrical power engineering. The opportunity to do the Master’s thesis at Saab have granted us insight in the engineering work-life and how life at Saab is. The team in which we’ve been employed have received us with open arms. Both the guidance and recommendations they’ve provided have been very insightful and their inclusion of us to the team has been outstanding. Some extra appreciation is in order towards our supervisors, Jacob Viktorsson and Daniel Samuel. Their guidance throughout the project has been very helpful and we are gratefully for all the time they spent guiding and discussing with us. Further we want to offer our thanks to our examiner Torbjörn Thiringer for all the assistance he’s given. Providing clear guidelines and helping us with the planning of a way forward when we at an early state of the project ran into certain holdups. Simon Larsson & Johannes Karlsson, Gothenburg, June 2023 vii List of Acronyms Below is the list of acronyms that have been used throughout this thesis listed in alphabetical order: BJT Bipolar junction transistor CCM Continuous conduction mode DCM Discontinuous conduction mode MOSFET Metal-oxide-semiconductor field-effect transistor PCB Printed circuit board PSFB Phase shifted full bridge PSU Power supply unit PWM Pulse width modulation RMS Root mean square ZCS Zero current switching ZVS Zero voltage switching ix Contents List of Acronyms ix 1 Introduction 1 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Technical aspirations . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Societal, ethical and ecological aspects . . . . . . . . . . . . . . . . . 3 2 Theory 5 2.1 Full bridge DC/DC converter . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Transistor design and selection . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 Parasitic elements . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.2 MOSFET losses . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Phase shifted full bridge operation . . . . . . . . . . . . . . . . . . . . 8 2.3.1 Zero-voltage switching conditions . . . . . . . . . . . . . . . . 10 2.4 Secondary side circuit design . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 Current doubler operation . . . . . . . . . . . . . . . . . . . . 12 2.4.2 Snubber design . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 Gate drivers for MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.1 Primary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.2 Secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.1 Magnetic design aspects . . . . . . . . . . . . . . . . . . . . . 17 2.6.2 Material selection and losses . . . . . . . . . . . . . . . . . . . 18 2.6.3 Leakage and magnetic inductance . . . . . . . . . . . . . . . . 19 2.6.4 Transformer windings . . . . . . . . . . . . . . . . . . . . . . . 20 2.7 Output capacitor and inductor . . . . . . . . . . . . . . . . . . . . . . 20 2.8 Converter waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9 Circuit controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.9.1 Adaptive delay . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9.2 Oscillator frequency and external clock . . . . . . . . . . . . . 24 2.9.3 Current control mode and slope compensation . . . . . . . . . 24 2.9.4 Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.9.5 Galvanic isolation . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.10 Feedback control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 xi Contents 2.10.1 Modelling of full bridge . . . . . . . . . . . . . . . . . . . . . . 26 2.10.2 Compensator network . . . . . . . . . . . . . . . . . . . . . . 27 2.10.3 Criteria for a stable feedback system . . . . . . . . . . . . . . 28 2.11 LLC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 Case set-up 33 3.1 Design process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2 Developing the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3 Construction of the converter . . . . . . . . . . . . . . . . . . . . . . 34 3.4 Verification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 Comparison with an alternative solution . . . . . . . . . . . . . . . . 34 3.6 Measurement setup and methodology . . . . . . . . . . . . . . . . . . 34 3.7 Converter specifications . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 Results 37 4.1 Phase shifted full bridge circuit design . . . . . . . . . . . . . . . . . 38 4.1.1 MOSFET selection . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.2 Primary side gate driver . . . . . . . . . . . . . . . . . . . . . 39 4.1.3 Secondary side design . . . . . . . . . . . . . . . . . . . . . . . 42 4.1.3.1 MOSFET gate driver . . . . . . . . . . . . . . . . . . 42 4.1.3.2 Snubber design . . . . . . . . . . . . . . . . . . . . . 45 4.1.3.3 LC-filter and bulk cap selection . . . . . . . . . . . . 45 4.1.4 Transformer Selection and design . . . . . . . . . . . . . . . . 46 4.1.4.1 Transformer parameters . . . . . . . . . . . . . . . . 49 4.1.4.2 Transformer loss estimation . . . . . . . . . . . . . . 49 4.1.5 Zero voltage switching capabilities . . . . . . . . . . . . . . . . 50 4.1.6 Feedback circuit design . . . . . . . . . . . . . . . . . . . . . . 51 4.1.7 Driver circuit setup . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2 Converter implementation . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.1 Circuitry changes . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.1.1 Snubber design . . . . . . . . . . . . . . . . . . . . . 58 4.2.1.2 Primary side inductor . . . . . . . . . . . . . . . . . 58 4.2.1.3 Transistor setup for primary side gate drivers . . . . 59 4.2.1.4 Optocoupler and error amplifier power . . . . . . . . 59 4.2.2 Converter performance . . . . . . . . . . . . . . . . . . . . . . 59 4.2.2.1 Converter efficiency . . . . . . . . . . . . . . . . . . 59 4.2.2.2 Converter waveforms . . . . . . . . . . . . . . . . . . 59 4.2.2.3 Mosfet waveforms . . . . . . . . . . . . . . . . . . . . 63 4.2.2.4 Visualisation of irregular switching pattern . . . . . . 64 4.3 LLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5 Discussion 69 5.1 Converter performance . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 Future improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3 Comparison to LLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6 Conclusion 73 xii Contents Bibliography 75 A Component data for circuit I B Pin layout of driver circuit III xiii Contents xiv 1 Introduction In recent years there has been a large focus on developing sustainable, reliant power systems [1]. A driving factor has been the transition towards renewable electricity generation for the power grid. The transition towards renewable power production has led to a focus on developing high power, high efficiency power electronic devices for the electric grid [1]. On the other hand, the same development has also enabled power electronics to efficiently power different loads for different applications. This advancement in technology has been a driving force for the project since some of Saabs technical solutions could benefit from an upgrade, considering the techno- logical advancements. Saab has requested an evaluation of a new converter solution for an existing application. The objective is to investigate if a new design could offer higher efficiency compared to the existing solution while at the same time providing a more customised design. The present solution consists of purchasing modules from an external producer which is not ideal considering cost and the dependency on the manufacturer. By producing the converter themselves, Saab could decrease the cost while simultaneously decreasing the dependency of external manufacturers for their products. 1.1 Purpose The purpose of this thesis is to investigate the possibility to replace the current power converter with a better converter. A phase shifted full bridge (PSFB) converter will be constructed and compared with an alternative solution consisting of an LLC converter. When comparing the converter designs the areas of interest are, but not limited to power capabilities and efficiency. The goal with the new design is a significant performance improvement compared to the already provided LLC converter, thus finding a reason for using a PSFB. 1.1.1 Technical aspirations The prototype will be designed according to the following technical specifications set by Saab: • Input voltage range from 350-400 V DC. 1 1. Introduction • Output voltage at 56 V DC. • Maximum power of 1200 W. • Maximum output voltage ripple limited to 1%. • Peak efficiency above 95%. 1.2 Goals Quantify potential advantages of using a phase shifted full bridge con- verter compared to the LLC converter. By studying and comparing the LLC converter module with a phase shifted full bridge converter, the aim is to determine if a new converter topology is overall advantageous and to which extent it might be more useful than the LLC solution. Thus, also determining shortcomings and limitations of using different converters. Aspects that need to be studied and quan- tified are power ratings and expected efficiency for different input voltages. Other important aspects to quantify includes voltage ripple, transient performance and number of modules needed. Design a realistic simulation model of the phase shifted full bridge con- verter. By constructing the circuit in a simulation software, it will be possible to get an indication for how the converter will perform and get a baseline for the performance compared to the specifications in section 1.1.1. Selection of Components. After studying the underlying functionality and de- termining the component requirements, all components will be selected accordingly with the goal to construct a functional PSFB. Construction of a working prototype of the converter. Using the simula- tion model as a guide, a physical prototype can be constructed with the selected components. The prototype will be tested and verified by comparing results to the simulated behaviour. The prototype should be stable and be able to be used for performance tests. Validate performance and compare to existing solutions. Ultimately a com- parison between the developed prototype and already existing solution will deter- mine if the PSFB converter has the potential to replace the existing technology. This would be verified by comparing the prototypes performance compared to the specifications in section 1.1.1. 1.3 Scope In order to make this project possible, some limitations must be set. The exclusion of electromagnetic interference (EMI) calculations and tests. EMI will be present since the circuit involves switching transistors. Since it 2 1. Introduction is a prototype board and there is time limitation for this project the circuit will not be designed to limit EMI. External disturbances on the primary side of the converter will not be considered. A general approach of designing the primary side will be used where the specifications required are in focus. The off chance that the power to the con- verter is disturbed will not be considered due to time restraints. Only the driver circuit LTC3722-1 will be used. Only the driver circuit LTC3722-1 will be investigated as a driver circuit for the converter since the report aims to investigate if a PSFB can be of interest. This driver circuit is specifically built for that application and will therefore be sufficient for the task at hand. Only two converters will be tested. The two converters to be tested consist of one LLC converter and one PSFB that will be designed and constructed for this project. The converters operates at different power levels and will therefore be studied at their rated levels to achieve a realistic performance comparison. There will only be tests conducted that are within the operation window of the converter during rated operation. A more comprehensive approach would include certain levels of power spikes outside of the rated power levels to ensure safe operations in case of some kind of disturbance. This will not be included in the report due to time limitations. Total cost of the converters will not be studied. The economical aspect will be considered profitable if the new converter is performing better, since the new converter will be constructed internally instead of by an external producer. Auxiliary power will be supplied externally. To decrease the number of com- ponents, complexity of the circuit and decrees the time needed to design the circuit, auxiliary power will be supplied from external power supplies. PCB design will be excluded. Due to time limitations the Printed circuit board (PCB) design will be conducted externally and therefore is not included in this project. However, the final design will be discussed in order to evaluate the converter performance and discuss future improvements. 1.4 Societal, ethical and ecological aspects There are severe ethical aspects associated to this project since Saab is a company mainly operating in the defence industry. This prototype could be a basis for future installations in Saab products, which might be used in future conflicts. However, it is also important to take into account that some countries might try to force other countries to comply to their agenda. A strong defence can be a tool for defending lives, liberties and independence. Environmental aspects mainly consist of E-waste from the components used. E- waste which is electronic components at the end of a use cycle can be problematic 3 1. Introduction since improper recycling could cause unnecessary waste and expose workers to toxic materials [2]. However unnecessary waste and exposure to toxic materials can be reduced by recycling properly and according to local regulations. 4 2 Theory 2.1 Full bridge DC/DC converter Full bridge converters are the standard for high power DC applications. Example applications for full bridge converters are chargers for electrical vehicles and to drive electrical motors [3]. The converter utilises four switches, T1 to T4 in Figure 2.1, on the primary side which allows both a positive and a negative voltage polarity across the transformer. Figure 2.1: A general DC/DC converter topology using a full bridge and current doubler design The switching pattern on the primary side of a conventional full bridge consists of three switching stages, where the switches are operated in pairs. In Figure 2.1 transistor T1 and T4 forms one pair whilst T2 and T3 form the other pair. The pairs will be turned on during a time period which depends on the converter switching frequency. When the pair is turned off, the other transistor pair will not immediately be turned on. The time period where no pair of transistors are conducting is called dead time and is there to avoid short circuiting the input source. After the dead time the other switch pair is turned on. The voltage over the transformer wingdings thus equals the source voltage but will flip polarity depending on which switching pair that is conducting. The result is a square wave with an amplitude of 2Vin peak to peak over the transformer. By using a transformer, the voltage on the secondary side can effectively be converted to a desired secondary voltage level with the advantage of having galvanic isolation from the primary side. However, the voltage on the secondary side of the transformer 5 2. Theory will have a similar waveform pattern as the primary side of the transformer. This consists of positive and negative square-waves with varying duty cycle. Therefore, there is an additional requirement to include a rectification process on the secondary side of the transformer to enable it for DC applications. Rectification on the sec- ondary side can be done by utilising either diodes or metal-oxide-semiconductor field-effect transistors (MOSFETs). 2.2 Transistor design and selection When designing high power converters there are mainly two different transistor types of interest, IGBT and MOSFET transistors. The two types differ in practical applications where the IGBT has a lower conduction loss but high switching losses. This causes the IGBT to be preferable in high current, low frequency operations, mainly below 20 kHz [4]. The MOSFET has a low gate capacitance compared to the IGBT, allowing for fast switching at low gate energies. Therefore, the switches in this converter will consist of MOSFETs since the converter is designed for high frequencies. A MOSFET can be controlled by applying a voltage over the MOSFETs gate and source pins. The MOSFET will then form a conducting channel between its drain and source pin. The voltage applied across its drain and source will limit how much current that can pass through the drain source channel. In general terms, a MOSFET can be seen as a voltage-controlled switch. 2.2.1 Parasitic elements MOSFETs are not ideal components, the switching time is not infinitely small and there are parasitic capacitors that needs to be charged and discharged to enable operation of a MOSFET [5]. The input capacitance correlates to how much energy that is required to turn on/off the transistor. A low parasitic input capacitance needs less energy to switch and can be operated faster for the same gate driver and same gate source voltage [6]. A MOSFET also contain a parasitic output capacitance in addition to the parasitic input capacitance. The parasitic output capacitance can cause the circuit to alter its behaviour by interfering with other components. The capacitance can, for example, in combination with an inductor cause high frequency ringing which could damage other components in the circuit and the MOSFET itself [5]. The output capacitance influences the behaviour of the MOSFETs, current can flow through the capacitance even though the MOSFET is off. The parasitic output capacitance also influences the time to turn off the transistor. A PSFB in comparison to a conventional full bridge is designed to discharge the output capacitance before switching in order to improve efficiency and utilise soft switching, which will be discussed in Section 2.3. 2.2.2 MOSFET losses A MOSFET is not an ideal switch or conductor, hence the non-ideal MOSFET will cause power losses when it is operating. Power dissipates as heat and the converter 6 2. Theory will therefore heat up. Limiting losses will limit how much the temperature will rise which in turn sets the requirements on converter cooling. Managing losses and cooling will increase the life span of the selected components. When a MOSFET is either turned on or off, there will be a short time interval where the transistor has a voltage across the drain source terminals and conducts current, as seen in Figure 2.2. Figure 2.2: Typical turn off waveform for a MOSFET. The overlap between current and voltage during switching is the switching loss. Switching losses are a significant portion of the overall losses for a MOSFET. To im- prove efficiency, soft switching could be implemented as in the case of a PSFB, which implements ZVS (Zero voltage switching). ZVS means there is no voltage across the transistor as it switches thus reducing losses and reducing the heat dispersed due to switching. Switching losses are calculated according to Psw = fsw ∫ vds(t)id(t) dt (2.1) where Vds is the drain to source voltage over the transistor, Id is the drain current through the transistor and fsw is the switching frequency of the converter [7]. The total amount of energy dispersed during a switch event can be calculated from (2.1) by neglecting to multiply with the switching frequency. Both turn on and turn off losses can be calculated in the same manner. Conduction losses in a MOSFET can be determined according to Pcond = RonI2 d (2.2) where Ron is the on-resistance for a MOSFET and Id is the root mean square (RMS) value for the current through drain to source. According to (2.2), conduction losses for a converter can be reduced by either using MOSFETs with lower on-resistance or by reducing the current through the MOSFET. Decreasing the current is a more effective approach to decrease the conduction losses since the conduction losses are proportional to the square of the current. By decreasing the current, the voltage must be increased to maintain the same power level, due to the relation between voltage and current according to P = UI (2.3) 7 2. Theory this relation offers the possibility to increase the voltage and therefore allow the cur- rent across the primary MOSFETs to be decreased leading to a decreased conduction losses. However, on the secondary side of the converter the voltage is kept constant and thus there is no possibility to decrease the current for a given load. There is however a possibility to use multiple MOSFETs in parallel in order to decrease the on resistance and thus also decrease conduction losses. 2.3 Phase shifted full bridge operation A PSFB builds upon the conventional full bridge whilst improving the efficiency by utilising soft switching. Soft Switching refers to the fact that the transistor will experience less stress and losses during a switching event since it switches when the voltage is close to zero [8]. In order to achieve ZVS a PSFB utilises a more complex switching pattern compared to a conventional full bridge [8]. The switching pattern for a PSFB converter is explained below. Figure 2.3 displays the current flow through the primary side when transistor A and D are conducting. When transistor A and D are conducting, the operation is identical as for a conventional full bridge. When MOSFET A and D are turned on, it possible to transfer energy from the source to the transformer windings [8]. Transistor A and D will conduct for a finite amount of time which is determined by the duty cycle and switching frequency. Figure 2.3: The first step of the ZVS switching sequence. When the first step of the switching sequence is over, only transistor D is turned off unlike the conventional full bridge where both A and D are turned off at this stage. Only turning off transistor D means that the voltage over transistor D starts to increase and will in effect charge the equivalent parasitic output capacitance of the transistor [9]. At the same time the voltage over transistor C will be zero since the potential will be the same on both sides of the transistor and the parasitic capacitance will therefore discharge the output capacitance of the transistor [10]. Current will flow through transistor A and the parasitic capacitance in transistor C and D as displayed in Figure 2.4. When the output capacitance of transistor C is discharged, the body diode of the transistor will conduct throughout the MOSFET [10]. Minimising this time period 8 2. Theory Figure 2.4: The Second step of the ZVS switching sequence. will limit power losses since conducting through the body diode causes power losses. The sequence when the body diode of transistor C is conducting is displayed in Figure 2.5. During the next step MOSFET C will be turned on and thus both MOSFET A and C will be turned on and effectively short the transformer winding. The current flowing thorough MOSFET C will not go through the body diode when MOSFET C is turned-on [10]. Since the output is shorted, there will be no power flow from the source to the transformer, but Current will instead flow in a circle according to Figure 2.6. Figure 2.5: The third step of the ZVS sequence. Figure 2.6: The fourth step of the ZVS sequence. MOSFET A will be turned off in the next step in preparation for activating MOS- FET B. When MOSFET A is turned off, the capacitor for MOSFET A will be charged whilst MOSFET B will be discharged [9]. The current will flow through MOSFET C and the parasitic capacitors for MOSFET A and B which can be seen in Figure 2.7. When the parasitic capacitance of MOSFET B is discharged, MOSFET B should immediately be turned on to achieve a soft switch [10]. If the MOSFET is not immediately turned on the body diode will conduct, and current will flow from the negative to positive input, which can be observed in Figure 2.8. Ideally this time instance should be as short as possible to avoid losses. When MOSFET B is turned on, the current direction will flip, causing the current direction to flow from the positive to the negative terminal, see figure 2.9 [10]. 9 2. Theory Figure 2.7: The fifth step of the ZVS sequence. Figure 2.8: The sixth step of the ZVS sequence. Figure 2.9: The seventh step of the ZVS switching sequence. At the point where transistor B and C are turned on, the converter has completed the transition from MOSFET A and D conducting to MOSFET B and C conducting. The converter will now repeat the same process but mirrored in order to activate MOSFET A and D again. The converter will cycle through all the above mentioned ZVS steps in order to decrease and limit turn on losses. Turn off losses will still occur for the converter between the first and second step of the ZVS switching sequence. 2.3.1 Zero-voltage switching conditions The condition required in order to enable ZVS for a converter is given by 4 3CossV 2 < 1 2Llki2 (2.4) where Coss is the parasitic capacitance of the primary MOSFETs, V is the voltage applied over the capacitance and Llk is the leakage inductance from the transformer which is discussed in Section 2.6.3 [9]. The expressing comes from that the inductive energy in the PSFB needs to be larger than the capacitive energy. Furthermore, the time required (freewheeling time) to obtain ZVS can be approx- imated using one fourth of the resonant frequency of the MOSFET and leakage inductance, see figure 2.10 [11]. 10 2. Theory Time Figure 2.10: Visualisation of the resonant frequency The figure presents how the voltage over drain to source decreases with a sinusoidal pattern when the gate signal switches to 0 V. The potential Vds reaches 0 V at T/4 for the sinus waveform marked as a dashed line in the figure. The resonant frequency can be obtained using fr = 1 2π √ Llk · 2Coss (2.5) The time required to enable ZVS can be obtained using TD ≥ π 2 √ Llk · 2Coss (2.6) 2.4 Secondary side circuit design To rectify the voltage and current from the full bridge, either a center-tapped or current doubler configuration can be used, the different circuits are presented in Figure 2.11 [12]. Figure 2.11: Left: Current doubler. Right: Center tapped The two approaches are more suitable for different applications, since the working principle is different. The current doubler offers easier transformer implementation on the secondary side with less copper losses, but instead requires two inductors. The current to the output can however be divided between the two inductors, resulting in 11 2. Theory half the RMS current in each inductor compared to using a center-tapped circuitry, see Figure 2.12. Time 0 C u rr e n t Figure 2.12: Waveform patterns for an equivalent center-tapped configuration compared to a current doubler. The trade-off for half the RMS compared to the center-tapped circuitry is that the current ripple at each inductor approximately doubles due to the halved frequency over each inductor. However, due to the possibility to divide the RMS current and the simpler design of the transformer with less copper losses, the current doubler will be further investigated in the project. 2.4.1 Current doubler operation The Current doubler operates using two inductors and two switches, for example MOSFETs. Depending on the polarity over the transformer, the current flows in different patterns. How the current flows is presented in Figure 2.13 [12]. Figure 2.13: Current flow patterns of a current doubler circuit. 12 2. Theory In the figure one of the rectifier MOSFETs are conducting where the red arrows symbolise the power transfer current through the transformer which is the current charging inductor Ls1. The blue arrow marks the current path through Ls2 which is the decreasing current due to discharge of Ls2. The time interval where the currents flow as in Figure 2.13 equals the time period when ILs1 increases and ILs2 decreases simultaneously in Figure 2.12. When the polarity over the transformer switches the other MOSFET starts conducting in the same pattern as the other MOSFET did, where Ls2 instead is charged and Ls1 discharged. This time interval instead equals the time period when ILs2 increases and ILs1 decreases simultaneously in Figure 2.12. A final state occurs when the voltage over the transformer is zero, resulting in no power transfer over to the current doubler secondary side. In this case both inductors are discharged through the MOSFETs according to Figure 2.14 and the time period equals the time where both ILs2 and ILs1 decreases simultaneously in Figure 2.12. Figure 2.14: Current flow patterns of a current doubler circuit. The current doubler can be operated in CCM (continuous conduction mode), where the current marked with blue arrows never stops before the polarity over the trans- former changes and therefore starts to instead charge the inductor Ls2 through the other MOSFET [13]. The current doubler can also operate in DCM (discontinuous conduction mode). This means that the inductor Ls2 runs out of energy before the polarity over the transformer switches and therefore eventually stops the flow of current through Ls2. 2.4.2 Snubber design The secondary side uses hard-switching MOSFETs, there is a possibility of LC resonances created during turn-off that could damage or destroy components. There are several options available for implementation in order to decrease the voltage spikes, all at various levels of power loss and complexity. One common approach is using a RC snubber in parallel with the MOSFET that causes the ringing [14]. This 13 2. Theory approach can significantly reduce oscillations, at the cost of increased power losses over the snubber. Another approach is the RCD snubber. The RCD snubber requires an additional component but reduces power losses in the snubber. Due to the diode, the RCD snubber can only protect against spikes of one polarity, leading to the requirement of two RCD snubbers in a full bridge configuration since the potential at the trans- former switches polarity. Both a general approach of an RC and RCD snubber can be observed in Figure 2.15 where the grey area "A1" and "A2" are the RCD snubbers and the grey areas marked with "B" are the RC snubbers. Noteworthy is that "A1" is connected to the input voltage of the converter in order to protect against positive voltage transients above Vin, whilst "A2" is connected to ground, protecting against negative voltage spikes. Figure 2.15: RCD and RC snubbers in a full bridge design 2.5 Gate drivers for MOSFETs The MOSFET in both the primary and secondary side require additional circuitry in order to function together with the converter. 2.5.1 Primary side The driver circuit LTC3722-1 shares the same ground as the input voltage on the primary side of the converter, therefore an output signal from the driver circuit on 14 2. Theory pins OutA to OutC (see Appendix B.1) is required surpass the voltage level of the source reference of MOSFETs A and C in order to trigger their conduction [15]. For the upper primary MOSFETs (A and C) in the PSFB the source voltage is floating and will change from 0 to 400 V depending on which lower transistor that is conducting. In order to power the gate of the transistors the gate voltage thus need to be able to fluctuate with source voltage and even surpass the source voltage [15]. However, the circuit driver can only supply an output voltage of approximately 10 V which is not sufficient to power the upper MOSFETS A and C. In order to power the said MOSFETs, a bootstrapping circuitry can be used [16]. This type of solution consists of a resistor, a diode and a capacitor combined with a gate driver. The general approach can be observed in Figure 2.16 Figure 2.16: Bootstrap design using a general gate driver The concept consists of using the capacitor Cboot as an energy storage, where it is charged from Vbias when the pin HS is connected to ground through the conducting lower MOSFET. This stored energy is then used as an extra voltage boost when the upper MOSFET is conducting, pushing the input pin HB to VS + Vbias. This setup ensures a voltage across gate and source to be equal to Vbias during on-time, assuming no voltage drop in Cboot when discharging. The size of Cboot that en- sures enough energy storage to accomplish bootstrapping can be found using the correlation Cboot > 10 · Cg. 2.5.2 Secondary side Since the MOSFETs are directly connected to the negative leg of the output volt- age, there are risks of a surge of negative current through the MOSFETs. This is commonly handled using circuitry that senses the current direction through the MOSFET and forces shutoff if it changes direction. One component of interest is the LTC3901 which can be used to accomplish this [17]. In order for this gate driver circuit to operate correctly and use the negative current protection, some external resistors are required, see Figure 2.17. 15 2. Theory Figure 2.17: Model of LTC3901 showing placement of resistors Where VG1 and VG2 is the gate signal for the two MOSFETs on the secondary side. VD1 and VD2 connects to the drain of the two MOSFETs. Thus VS1 and VS2 connects to the source leg of the transistors. The resistors RCSX1, RCSX2 and RCSX3 can be calculated using k = (48∆I · RDS.on) − 1 (2.7) RCSX2 = 200Vin.MAX · Ns Np − 2200(1 + k) k (2.8) RCSX1 = k · RCSX2 (2.9) RCSX3 = RCSX1RCSX2 RCSX1 + RCSX2 (2.10) ∆I is the peak-peak current ripple in the output inductors, RDS.on is the conduction resistance of the MOSFET controlled, Ns and Np is the secondary and primary windings of the transformer. LTC3901 can directly power the MOSFETS from the gate signal without a boot- strapping circuit since the soruce pin of the MOSFETs are referenced to ground in a current doubler circuit. LTC3722-1 provides the main control of the gate signal used for MOSFET E and F but LTC3901 powers the amplifies the gate signal with the added current protection as mentioned above. LTC3722-1 however is placed on the primary side of the converter and therefore does not share the same ground as the secondary side due to the galvanic isolation. Therefore, a middle step like a transformer can be added to the two circuits can communicate properly. 2.6 Transformer design The use of a transformer allows for power transmission whilst isolating the input from the output. By using a transformer, the converter voltage and current can be scaled to the required levels by changing the turn ratio [18]. The turn ratio is the ratio between the number of turns on the primary side and the number of turns on 16 2. Theory the secondary side. For a secondary side current doubler rectifier, the turn ratio N is determined according to N = Vin(min)Dmax 2Vout (2.11) where Vin(min) is the lowest possible input voltage, Dmax is the highest possible duty cycle, Vout is the desired output voltage [12]. A lower turn ratio will give a higher secondary voltage for a given input voltage. Which in turn lowers the maximum duty cycle needed [18]. 2.6.1 Magnetic design aspects When designing a transformer it is important that the magnetic core does not satu- rate. When a magnetic material saturates it means that the magnetic permeability of the material changes which disrupts the linear relationship between the magnetic field and the flux density, as seen in B = µH (2.12) where B is the magnetic flux density, µ is the magnetic permeability of the core material and H is the magnetic field strength. The magnetic flux density has also reached a maximum value when a core saturates. A saturated core can damage components in the circuitry since the primary side current increases when the core saturates [19]. To avoid saturation, the primary wingdings need to be designed in such a way that the peak magnetic flux density is always lower than the saturation flux density level for the material. Limiting the magnetic flux density will also limit core losses. The flux swing of the transformer is determined according to ∆B = V DT NpAe (2.13) where V is the applied voltage over the primary transformer windings, D is the max- imum allowed duty cycle and T is the switching period as seen from the transformer, where the transformer will experience half the switching frequency compared to the oscillator of LTC3722-1 [15]. Np is the number of primary turns on the transformer and Ae is the effective area for the transformer. The numerator of (2.13) can be seen as the volt-second product for the transformer which is equivalent to the magnetic flux through the transformer core [20]. Since the voltage over the transformer will be both positive and negative for an equal time interval during a switching cycle, the average magnetic flux will be zero over the core, whilst the magnetic flux density will swing in accordance with (2.13). The peak magnetic flux density will therefore be half of the magnetic flux density swing. Therefore, if the peak magnetic flux density is lower than the given saturation limit for the core material, the core will not saturate [18]. Small voltage deviations for different pulses can cause an equivalent DC offset for the voltage. These deviations can be caused by differences in the MOSFET manu- facturing [21]. The small offset will cause the flux density to slowly increase towards 17 2. Theory saturation. The imbalances can be solved by applying current control mode to the circuit [21]. Current limitation is an essential feature to avoid transformer satura- tion. When a core is close to saturation, the primary current will rise quickly, which will be sensed by the controller. If the set current limit is exceeded, the switching cycle will be terminated and thus avoids damaging the converter [19],[21]. 2.6.2 Material selection and losses The material selected for the core depends on the use case, where ferrite is typically used for switching converters [6]. Ferrite is suitable at high frequency operation due to low hysteresis and low Eddy current losses, compared to other magnetic materials. A drawback with ferrite is that it saturates for lower magnetic flux density compared to other magnetic materials and can thus not be magnetized as much as other materials. The hysteresis can be seen from the materials B-H curve, where the B-H curve follows the relation in (2.12). For a ferrite core, hysteresis is the dominating core loss, other losses such as Eddy current losses are negligible due to high electrical resistivity of the material [6]. The hysteresis loss for a core is dependent on the overall volume of the core, flux density, temperature and frequency [6]. The hysteresis loss can be determined from studying data sheets from the core manufacture which often gives the specific power loss as a function of frequency and magnetic flux density [22]. Except for the magnetic losses, copper losses from the winding’s are prevalent and will determine the overall effectiveness of the transformer together with the magnetic losses. The copper losses originate from the ohmic losses of the long copper windings, which can be determined using Pcu = i2R (2.14) where i is the RMS value of the current through the windings and R is the resistance of the wire. The resistance can be determined when the length, area and conductivity of the material is known, according to R = ρ l A (2.15) The length of the wire depends on both primary and secondary side number of turns and the turn ratio between them. The circumference around the core also determines the overall length of the windings. Losses where the current is high yields higher losses according to (2.15). By decreasing the number of turns the ohmic losses will decrease, but from (2.13) it can be seen that increased number of turns will allow for a lower flux density swing and therefore lower magnetic losses, resulting in an optimisation problem. To minimise overall losses, the resistivity of the windings can be decreased to further increase efficiency. However, decreasing the resistance is not as trivial as increasing the conducting area, since the available space for the wingdings is limited. 18 2. Theory Skin effect, an effect occurring when using high frequency current, will limit the conduction area and therefore the resistance of a conductor since current will only flow close to the surface of the conductor [6]. The depth at which the current penetrates due to skin effect can be determined as δ = √ 2 2πfµ0µrσ (2.16) where δ is how deep into the conductor current will penetrate in the material, µ0 and µr is the magnetic permeability for air and the relative magnetic material respec- tively. σ is the conductivity of the material [6]. The overall effective conducting area determines the resistance and the losses. One approach to have a large conducting area is by using litz wires, which are small conducting wires bundled together but isolated from each other, resulting in a reduction of the skin effect [18]. 2.6.3 Leakage and magnetic inductance A real model of a transformer includes several parasitic parameters, such a model is displayed in Figure 2.18 [6]. Resistances R1 and R2 are the respective winding resistances from the primary and secondary windings. Llk1 and Llk2 is the leakage inductance for the primary and secondary side of the transformer. Leakage induc- tance arises from a transformer when magnetic flux from the primary coil leak and does not reach or link with the secondary side coil [6]. Normally, leakage inductance should be minimised to avoid overvoltage and LC resonances, however for a PSFB, leakage inductance is used to discharge the parasitic capacitance’s of the MOSFETs in order to achieve ZVS. Lm is the magnetizing inductance through the core, and the current through Lm is the magnetizing current which is used to magnitize and maintain flux inside the core [23]. Rm is a symbolic resistance that represents the hysteresis losses through the transformer. R1 Llk1 LmRm N1:N2 Llk2 R2 Figure 2.18: A circuit of a non-ideal transformer Llk1 and Lm can be determined by performing open-circuit and short-circuit tests on the transformer [24]. Conducting an open-circuit test means measuring the in- ductance on the primary winding when the secondary winding is an open line. This test provides the sum of Llk1 and Lm. A short circuit test is conducted by short- circuit either side and measuring the inductance on the other side, resulting in a measurement of Llk1 or Llk2. Thus, by subtracting the result from the short circuit 19 2. Theory test to the open circuit test, the magnetizing inductance can be determined [24]. Ideally the magnetizing current should be as small as possible, in an ideal case there is no magnetizing current due to a perfect core material that does not need energy to stay magnetized, in the ideal case the permeability of the core is infinite and the magnetizing inductance is also infinitely large. 2.6.4 Transformer windings The physical dimensions of a transformer also needs to be considered in the design process to be able to have enough physical space to fit the windings. Transformer cores comes in different sizes and shapes in order to fit different use cases. The core type and size needs the be selected in accordance to limit the aforementioned winding and core losses. The windings should fit around the transformer and through the window area of transformer. The window area is a cross-sectional area where the windings are supposed to wound. The window area should be larger than the total amount of conducting area for both the primary and secondary windings and also have enough space for electrical isolation between the primary and secondary windings. The window area for a typical E-core is displayed in Figure 2.19. Figure 2.19: Window area of a E-core transformer. 2.7 Output capacitor and inductor In order to filter and reduce the ripple to a DC signal on the output current and voltage, output capacitors and inductors are required. The output current ripple should be small in comparison to the DC value of the output current, since the magnitude of the ripple decides the stress over the capacitor [25]. One approach to decide the limit of allowed current ripple is to use an inductor large enough to avoid operating in DCM at the rated power levels of the converter, since the gate driver LTC3901 is mainly designed for CCM [17][11]. Using the lower limit of power output with the output voltage gives the lowest DC current output 20 2. Theory according to Iout.min = Pout.min Vout (2.17) where the current is evenly shared over the 2 inductors Ls1 and Ls2 in Figure 2.11. Due to the shared current between the inductors, the maximum ripple allowed to ensure no negative currents equals the magnitude of the output current. Using this limit the size of the inductors required can be determined according to LS = 1 ∆ILS.pp Vout(1 − ph)T (2.18) where ∆ILS.pp equals the inductor current ripple and T is the period time for the transistors. The parameter ph is the effective phase shift and can be calculated using ph = VoutNp VinNs (2.19) where Np and Ns are the primary and secondary windings of the transformer. When designing the output capacitor, the internal ESR (equivalent series resistance, notation Rc) is of importance, where the amount of ESR will determine the losses over the capacitor according to PCout = I2 Cout.rms Rc (2.20) This loss will decrease the efficiency of the circuit but also risk overheating the capacitor, which must be taken into consideration when selecting capacitors. The amount of ESR of the output capacitor will also determine the voltage ripple of the output during steady state, with the relation Rc = ∆Vout ∆ICout (2.21) where ∆Vout is the allowed voltage ripple over the load [26]. The current ∆ICout is the peak to peak ripple current for the bulk capacitor, which can be calculated using ∆ICout = Vout LS T (1 − 2ph) (2.22) Thereafter the output capacitor can be determined with the calculated requirement of maximum ESR allowed. 2.8 Converter waveforms With the presented components from previous sections, the correlation between dif- ferent components and their corresponding waveform can be studied. The waveforms of the PSFB are presented in Figure 2.20. The waveforms are simplified in order to provide a clear picture of its operational pattern of the PSFB. Signals VG−A to VG−D 21 2. Theory is the gate signal for the four MOSFETs in the full bridge. Signals VG−A and VG−B are part of the passive leg of the converter [15]. VG−C and VG−D are part of the active leg of the PSFB. Active leg means that the signals are actively controlled to allow for a certain overlap to MOSFET A and B of the passive leg. This means that MOSFET D is modulated to overlap MOSFET A for a certain time, and the same for MOSFET C which is modulated to overlap MOSFET B. The overlap involves the switching pattern of the PSFB as presented in Section 2.3. The overlap is seen as a phase shift and hence the name of the converter topology. The transformer voltage correlates to the switches that are turned on and off [27]. By altering the phase shifting the pulse width of the transformer voltage can be increased or decreased. The same is true for the primary side transformer current where the pulses will form more of a triangle shaped pulse with increased load. Note that the transformer voltage is bipolar, meaning that the upper value of the voltage in 2.20 corresponds to the positive input voltage whilst the lower edge corresponds to negative input voltage over the transformer. The same is true for the current through the transformer. The secondary side MOSFETs can be powered on simultaneously if there is no volt- age over the transformer [15]. When both are conducting the transformer secondary side is shorted, but since no energy is transferred from the primary side due to the voltage over the primary winding is zero. When there is voltage over the transformer only one transistor can be turned on. The current over the inductors are also linked to when there is voltage over the transformer and the secondary MOSFETs are conducting [11]. A positive current slope for inductor LS2 occur when MOSFET F is conducting and the transformer voltage is positive. And for inductor LS1 a positive current slope occurs when MOSFET E is turned on and the transformer voltage is negative. 22 2. Theory V G -A V G -B V G -C V G -D V G -E V G -F V P ri m a ry I P ri m a ry I L S 1 I L S 2 Figure 2.20: Characteristic waveforms of components in a phase shifted full bridge. 2.9 Circuit controller In order to control the gates of the PSFB converter, the driver circuit LTC3722-1 from Analog Devices will be implemented [15]. The circuit controller both have features that influence other components and will determine how the converter is implemented. 23 2. Theory 2.9.1 Adaptive delay The controller includes options to have an adaptive delay for MOSFET switching in order fix the timing for ZVS [15]. By including the switching delay for the MOSFET in combination with the gate driver delay the controller can anticipate when to switch in order to achieve accurate ZVS. The controller measures the input voltage and the voltage on the passive and active leg of the full bridge. The controller also includes a maximum delay where it will try to achieve ZVS since ZVS might not be possible for all load conditions and thus will only wait for the maximum set delay before switching. 2.9.2 Oscillator frequency and external clock The internal oscillator of the driver circuit can be set to a maximum frequency of 1 MHz depending on the application [15]. The frequency is determined by placing a capacitor which will repeatedly be charged and discharged. The circuit also allows for use of external clocks if the converter is to be used in combinations with other converters. Paralleling more than one converter allows for current sharing and more converters can thus be stacked in parallel to increase the power range. By coupling two converters they can be configured to be out of phase to each other in order to have a more even power delivery. 2.9.3 Current control mode and slope compensation The LTC3722-1 uses peak current mode control which means that the current on the primary side of the converter is monitored in order to control the converter [15]. The current is monitored by placing a resistor on the source leg of the lower MOSFETs in the full bridge and measuring the corresponding voltage over the resistor. The input from the current sense and the input from the feedback circuit is compared in order to determine an appropriate value for the PWM modulation. The circuit can thus instantly detect if the current is abnormal such in the case of a saturated transformer. Current mode control will also alter the behaviour of the converter which will influence the feedback system which is discussed in Section 2.10.1 [28],[29]. Drawbacks with peak current mode compensation include that current spikes due to switching noise can trigger the set current limit [28]. Faulty triggering due to switching noise can be mitigated by implementing a blanking period which effec- tively turns off the current sense during a programmable time interval when the converter is switching. When utilising peak current mode control, subharmonic oscillations might occur and cause instabilities when the duty cycle is over 50%. The subharmonic oscillations are a natural part of controller utilising peak current mode, but can be mitigated by the use of slope compensation which is the case for LTC3722-1. The circuit controller introduces a small current to correct for the subharmonic instabilities. Both the blanking time and slope compensation is set when designing the circuit in order to operate correctly for the specific use case. 24 2. Theory 2.9.4 Circuit protection The controller includes several protection mechanisms to ensure safe and stable protection of the circuit [15]. The limits need to be set by the designer in a proper manner to ensure that the safety features works as intended. The circuit monitors the input voltage and will stop operating if the voltage is too low. The current will also be monitored and the circuit will firstly turn off the switching state, but if the current is consistently over a threshold, the controller can restart the circuit by initialising a soft start. A soft start in the case of the LTC3722-1 means that it is current-limited and thus will slowly ramp up the current in order to not overload the circuit at start up. 2.9.5 Galvanic isolation Since there are large voltage differences between the primary, secondary sides, there is a need for physical isolation between the two circuits areas mentioned. The approach that will be approached in this report is by using transformers and an optocoupler. The optocoupler will be required for the feedback signal required for the driver circuit, since its input is acquired directly from the output voltage. The optocoupler will take an input voltage and adjust its output accordingly. This transfer occurs in the optocoupler by emitting light depending on the input to a receiver on the output [30]. 2.10 Feedback control When implementing a converter, it is important to study how the converter can handle load transients since the converter does not always operate in steady state or with a constant load. A converter should be able to respond in a controlled manner to load steps and load surges to ensure a stable output voltage level. The response time is crucial since too slow response times can result in severe output voltage deviations, while a too fast system might result in an unstable output voltage oscillation. When the load changes, the output voltage will initially rise if the load drops, or decrease if the load increases. By monitoring the change in voltage it is possible to regulate the PWM (pulse width modulation) signal on the primary side MOSFETs in order to correct the output voltage. Connecting the output back to the PWM modulator involves creating a closed control loop of the converter. The connection from output to the modulator must be connected through an error amplifier in order to translate the output voltage to a voltage level that can be interpreted by the control circuit LTC3722-1 in order to regulate the voltage. A typical block scheme of the control loop can be seen in Figure 2.21. 25 2. Theory Circuit Controller Full bridge Converter Compensator network Vo Figure 2.21: Control loop for a PSFB 2.10.1 Modelling of full bridge In order to construct a compensator circuit, the transfer function characteristics for the PSFB must be determined first, in order for the compensator network to be effective. Important aspects that need to be determined before the designing the feedback system is the output filter. In the case of a current doubler the output filter consists of an output capacitance two inductors in parallel. Another important aspect for the feedback system is the type of control mode used by the control circuit. Common control modes are peak current mode, average current mode and voltage mode [31]. When using any of the two current mode controllers, the converter will consist of two control loops, one inner current loop and the outer feedback loop that will regulate the output voltage specifically. The LTC3722-1 used for this converter uses peak current mode which will slightly alter the behaviour of the converter [15], [32]. Peak current mode reduces the noise immunity compared to average current control mode but has other advantages such as detecting current faults earlier as in the case of transformer saturation. Voltage mode control only is severely slower to detect errors that peak current mode. Current control mode which is discussed more in detail in section 2.9.3. To model a PSFB with a current doubler, the converter behaviour will be somewhat simplified in order to be able to derive a transfer functions of its behaviour, where the circuit is linearized with a small signal circuit equivalent. From [33]-[34] the PSFB transfer function can be modelled as vo d = RloadVin NLCoutR2 · (1 + RcCouts) s2 + (R1 L + 1 CoutR2 )s + 1 LCout (R1 R2 + (Rload R2 )2) (2.23) where Rload is equivalent load resistor, L is half of the output filter inductors due to the fact that a current doubler uses two inductors in parallel [33]. Rc is the equivalent series resistance of the output capacitor. R1 och R2 can be determined as R1 = Llkf N2 + RcRload Rc + Rload (2.24) R2 = Rload + Rc (2.25) 26 2. Theory Where Llk is the leakage inductance and f is the switching frequency experienced by the transformer. 2.10.2 Compensator network A compensator network is added in order to close the voltage loop from the output, back to the circuit controller and also compensate the PSFB in order to achieve a stable operation [35]. The compensator network consists of an error amplifier and the complexity of the compensator network depends on the gain and phase of the converter. The compensator is designed whilst knowing the behaviour of the converter from (2.23) in order to create a stable feedback system [15]. The compensator is designed in order to compensate for the converter behaviour by placing the poles and zeros of the compensator in accordance with the converter. Generally, the compensator should be designed in such a way that the crossover frequency of the system is placed before the zero created by the output capacitance ESR, which is the numerator of (2.23) [15]. The crossover frequency should be placed with a margin to the ESR zero, however, what frequency margin to use is impossible to determine, since small deviations in for example ESR causes the zero to be moved substantially. A type III regulator can be seen in the Figure 2.22. The type III compensator network is regulated and adjusted by selecting the values of the components in the regulator. R1 R3Vref R2 C1 C3 C2 R4 V0 Vcomp Figure 2.22: Type III regulator The type III compensator in Figure 2.22 has three poles and two zeros which can be determined as fz1 = 1 2π(R1 + R2)C1 (2.26) 27 2. Theory fz2 = 1 2πR4C2 (2.27) fp0 = 1 2πR1(C2 + C3) (2.28) fp1 = 1 2πR2C1 (2.29) fp2 = 1 2πR2 ( 1 C2 + 1 C3 ) (2.30) Each of these poles and zeros combined with the poles and zeros of the converter in order to combine and create a stable feedback system. A type III compensator will thus have an asymptotic Bode plot and phase response characteristics as displayed in Figure 2.23 and 2.24. fp2 will appear at a high frequency where the converter will likely be attenuating signals and the influence of C3 is negligible and can be disregarded [15]. A type III regulator has a phase boost which will improve on the phase margin of the system in order to keep it stable. Frequency (Hz) G a i n ( d B ) f p0 f z1 f z2 f p1 f p2 Figure 2.23: Bode plot of type III compensator Frequency (Hz) P h a s e ( d e g r e e s ) Figure 2.24: Bode phase plot of a type III regulator 2.10.3 Criteria for a stable feedback system By compensating poles and zeros of the converter with the compensator network, the gain and phase of the system can be specified during the design phase, and a stable feedback system can be created. Important characteristics of the feedback system is the gain crossover frequency which is the point where the gain crosses the zero dB in amplification [36]. All frequencies below the crossover frequency will be amplified whilst all frequencies above the crossover frequency will be attenuated. In general, placing the crossover frequency at higher frequencies will make the converter quicker to respond to variations of the load but might also make the converter overshoot if it is too quick. The phase margin of the converter, which is the phase difference from -180°at the gain crossover frequency is also important [36]. It is a indication of stability of the system. A phase margin of 45 to 60 degrees could be considered stable. 28 2. Theory 2.11 LLC converter The LLC converter is similar to the PSFB construction, utilising either a full-bridge or a half-bridge on the primary side of the converter [37]. There is one significant difference from the PSFB however, the LLC tank. This additional setup presented in Figure 2.25 enables soft switching due to the generation of resonance behaviour. The PSFB instead uses a phase-shifting control to achieve ZVS. Figure 2.25: LLC The LLC tank will generate a sinusoidal current waveform with the frequency equal to the switching frequency of the square-wave fed to the LLC tank from the full bridge, offering a possibility of soft switching operation. Both ZVS and ZCS is possible when the switching frequency equals the resonant frequency of the LLC tank, which can be defined as fr = 1 2π √ LrCr (2.31) where Lr and Cr are the resonant components presented in Figure 2.25. Since the LLC converter can achieve both ZVS and ZCS at the resonant frequency, the LLC converter is generally designed to operate at the resonant frequency during nominal operation in order to maximise the efficiency. The LLC has two additional operational regions apart from operating at resonance frequency: Below resonance and above resonance, visualised in Figure 2.26. In this Figure multiple gain functions has been plotted with different values of the quality factor Q. The quality factor can be determined using Q = √ Lr/Cr Rac (2.32) Rac = 8N2 p π2N2 s Rload (2.33) 29 2. Theory Rload = V 2 out Pload (2.34) It is observable that the quality factor has a linear relation to the load and therefore gives the behaviour of the system during different load conditions. The region when the LLC operates below the resonance frequency occurs when the input voltage is lower than the output voltage. Operating below the resonance frequency is when the risk to enter capacitive mode is largest. During capacitive mode ZVS is not possible, but ZCS can instead be achieved. This is however in most cases not preferred over ZVS due to large voltage spikes occurring when MOSFETs are hard switching. The converter will operate above the resonance frequency when there is a larger input voltage than the output voltage. The frequency of the switching will vary when load steps occur, where the load rapidly changes. A general approach to ensure resonant frequency during nominal operation is to define the turns ratio of the transformer accordingly. Figure 2.26: LLC A design parameter that is of interest for LLC converters is the lowest power rating the converter is supposed to deliver. This parameter is of importance since light loads risk to set the LLC into the capacitive region during voltage drops at the load, ultimately resulting in current leading the voltage in phase. In this operation ZVS cannot occur and there is also risk of generating large current spikes during switching that can result in device failure. However, the converter can also be designed to operate in the capacitive region and could be operated with zero current switching (ZCS). An LLC converter in comparison with the PSFB is operated with a variable switch- ing frequency to achieve different gain for different scenarios according to Figure 2.26. Varying the frequency to achieve ZVS and ZCS implements another level of 30 2. Theory complexity compared to only the PWM modulation in the PSFB. The frequency is controlled by modulating the gate signal on the primary side bridge configuration [38]. Modulating the frequency can decrease the switching losses when using ZVS and/or ZCS, however frequency modulation can also cause other components to in- crease their power losses. When operating far from the resonant frequency, current in the converter will increase which in turn will increase conducting losses. Also, the transformer losses will vary depending on frequency, higher frequency will cause higher core losses but lower frequencies will magnetize the core harder and thus also cause increased core losses. So, in the case of an LLC, the magnetic components needs to be designed to keep the losses at a minimum for a wide frequency range. For the LLC it is therefore important to compare if it is beneficial to always operate with soft switching or if other components might decrease the efficiency instead. Current sharing LLC converters can be cumbersome due to the frequency depen- dence compared to the fixed frequency. With resonant converters the tolerances of the components will vary the resonant behaviour which can make the converters have different gain for different frequencies [39]. In such a case the converters will not equally share the load. To better balance the power delivery more complex control strategies would have to be implemented [40]. 31 2. Theory 32 3 Case set-up The project consists of five main objectives: design, develop, construct, verify and compare the PSFB converter. The aim is to reach the goals stated in chapter 1.2 3.1 Design process There is a requirement to follow several design limitations when designing the circuit meant to replace the present converter solution. The design limitations exists partly since Saab has already ordered some components in order to save time. Other design limitations exists to ensure that converter is suitable for the application that it is supposed to be used for. The project will investigate the usage of a phase shifted full bridge as the circuit design, with the driver circuit LTC3722-1 used to operate the converter [15]. The main design task is to design a functional phase shifted DC/DC converter for the given operational requirements. The selection of components and implementation of the driver circuit will be an essential early step in the project process. The design of the converter will be influenced by the data-sheet of the driver cir- cuit LTC3722-1 provided by Analog devices, the manufacturer to the driver circuit. Furthermore many design choices will be implemented with the aid of calculations and research in scientific reports. 3.2 Developing the circuit A circuit model will be constructed, simulated, tested, further developed and ver- ified. This will be conducted using LTspice, a simulation software published by Linear Technologies, now part of Analog devices. Caution will be taken when con- sidering the obtained results due to the fact that simulations often miss problems that occur in the physical hardware. All simulated components are to some degree ideal, resulting in non-realistic results. 33 3. Case set-up 3.3 Construction of the converter Eventually the required components will be ordered after sufficient simulation data has been obtained. There will also be a requirement of designing a transformer with the availability to arrange order of windings, allowing for more flexibility when calibrating the output voltage during the construction of the prototype. The full bridge circuit will be constructed using the selected components and the LTC3722-1 driver circuit according to the final design model. Tests will be conducted in parallel with the construction to ensure that construction errors are excluded. 3.4 Verification process Finally there will be a verification process of the circuit board. During this process, measurements will be conducted to ensure operation within the required specifica- tions. The obtained data will be used to analyse the differences in performance compared to the prior solution. Interesting parameters to verify includes the output voltage and current ripple as well as the input and output voltages and currents to enable efficiency measurements. The verification process will involve a risk of electrical shock, since there will be high voltages up to 400 V DC present during operation of the circuit. To eliminate risking the health to the person/persons conducting the verification, all tests are done in accordance to safety regulations for high voltage applications. 3.5 Comparison with an alternative solution There will be an interest in comparing the final product with another solution for its given task to ensure the legitimacy of the constructed PSFB. The other solution that this PSFB will be compared to is a LLC converter. The LLC converter is designed towards another power level and therefore the comparison will be tested at the rated values of each converter in order to ensure adequate comparison of their operation. Areas of interest when comparing the solutions consists of mainly efficiency, amount of output disturbance, load variation response and design complexity. 3.6 Measurement setup and methodology In order to verify and compare the converters against each other, certain measure- ments of the converters were required. The general setup of how the converters were connected is presented in Figure 3.1. The power supply unit (PSU) were set to desired voltage level to power the converter. The converter is powering a current controlled DC electronic load where the current is adjusted to meet the desired out- put power of the converter. In order to make the PSFB converter operate it requires 34 3. Case set-up a 12 V input signal to its driver circuits, therefore an additional PSU is used to feed the primary and secondary side of the converter individually. the two separate 12 V signals are isolated from each other in order to maintain the galvanic isolation. This signal side PSU is not required for the LLC converter since the signal is generated internally through an extra transformer setup. Figure 3.1: The general approach of how the converters were tested The PSFB converter was measured in several different approaches, where all the positions used for the measurement instruments are presented in Figure 3.2. Note- worthy is that the current measurement was conducted using a clamp-on current probe in order to disturb the circuit as little as possible. The LLC converter was only tested by measuring the input and output voltages and currents, which allowed for an efficiency approximation. Figure 3.2: Placements of voltage and current measurements of the PSFB converter 35 3. Case set-up 3.7 Converter specifications This section includes the ratings of the converter used for this project. The nominal PSFB ratings are displayed in Table 3.1. Table 3.1: Phase shifted full bridge specifications Value Unit Pmax 1.2 kW Vin.min 350 V Vin.max 400 V Vout.nom 56 V fmin 200 kHz The specifications of the LLC converter that the PSFB converter was compared against are presented in Table 3.2. Table 3.2: LLC specifications Value Unit Pmax 5 kW Vin.min 340 V Vin.max 500 V Vout.nom 29 V fmin 170 kHz fmax 230 kHz 36 4 Results In this chapter the results of the design choices selected for the PSFB are presented. The design choices are based on the theoretical background. Thereafter the mea- sured results on the physical converter is presented. Due to an error in the current sense feedback loop, the converter was tested up to an input voltage of approxi- mately 200 V and a maximum output power of 400 W. At the end of this chapter, the performance of the LLC converter is presented. 37 4. Results 4.1 Phase shifted full bridge circuit design The designed circuit schematic for the PSFB converter can be observed in Figure 4.1, more in depth results will be presented in more detail further along in the chapter. More information regarding the components can be obtained from appendix A.1. Figure 4.1: Circuit design including all components. 38 4. Results 4.1.1 MOSFET selection The transistors used for the circuit are MOSFETs SCT4026DW7TL, developed by ROHM Semiconductors for the primary side. This decision is based on conduction losses, low output capacitance and sufficient breakdown voltage to survive input voltages with transients. The setup consists of one MOSFET for each gate, 4 in total for the primary side. Each of the MOSFETs have an on-resistance Rds of 26 mW. The parasitic output capacitance for one MOSFET is 111 pF, which can be determined by studying the data sheet of the MOSFET. The conduction loss for one transistor can be determined to 0.32 W using (2.2) for an ideal converter with an input voltage of 350 V and output power of 1200 W. Switching losses for the MOSFET are presented in Section 4.2.2.3 where the actual MOSFET waveforms are presented. The transistor chosen for the secondary side was the MOSFET UF3SC065030B7S, developed by UnitedSiC. In this case a total of three MOSFETs are connected in parallel per side which can be seen in section C in Figure 4.1. This design of using three per signal gives a reduced conduction loss due to the decreased Rds, see (2.2). Dissipating the losses over three MOSFETs will also decrease the temperature development per MOSFET. The trade-off will be that this setup increases the total capacitance of the equivalent MOSFET, but this is a sufficient trade-off since the secondary side draws large amounts of current. Further the capacitance value is most important for the primary side since it affects the availability to enable ZVS, which the secondary side MOSFETs does not influence. The on-resistance Rds for one of the MOSFETs on the secondary side is 27 mW, resulting in a total of 9 mW for each signal when using three in parallel. The Conduction loss for each MOSFET trio can therefore be determined to 2.65 W using an RMS current of 16 A determined from simulations. 4.1.2 Primary side gate driver In order to enable the gate signal to reach a potential where it surpasses the MOS- FET source signal for Q1 and Q3 in Figure 4.1, the bootstrapping driver LTC4440 will be used [41]. The LTC4440 usually has a 100 V limit when TS is referenced to ground. But by connecting TS together with LTC4440s ground to the source leg of the MOSFET, the LTC4440 will have the same reference as the MOSFET. However, the signal from the driver circuit LTC3722-1 thus needs to be isolated by using a signal transformer in order to make the design function, see T2 and T3 in Figure 4.1. Diodes and resistors are connected to the input signal according to R1, R2, D3 and D4 with the purpose of limit the current flow into pin INP while also enable a direct connection to the floating reference ground for the signal transformer to enable discharge of energy stored in the signal transformer, see Figure 4.2. 39 4. Results Figure 4.2: Circuit design for implementation of LTC4440 mattering MOSFETs Q1 and Q3 The external supply voltage of 12 V will be protected using diode D1, where the 12 V signal will be forwarded to the MOSFET gate through transistor Q13 when an on- signal is obtained from signal A. During turnoff the gate will instead be connected to the source leg through Q17. By using the setup of Q13 and Q17 to send a 12 V signal to the gate of Q1 instead of directly connection output pin TG to the gate of Q1 removes the restriction of maximum current flow from the gate driver circuit LTC4440 and instead places the current restriction only upon the 12 V power supply when enabling Q1. This setup potentially allows for faster switching due to a faster gate charge of Q1. D5 offers extra protection for the MOSFET, intending to limit the maximum voltage applied between gate and source. R5 is added before the gate of the MOSFET in order to control the switch speed by limiting the current flow, essentially to regulate turn on/off oscillations at the cost of efficiency. C1 plays a crucial role in order to ensure 12 V to boost according to the bootstrapping method mentioned in chapter 2.5.1. The complete implementation to the final circuit for gate signals A and C is marked with "A" in Figure 4.1. The circuitry surrounding LTC4440 for signals B and D will be similar to the cir- cuitry for signals A and C, however some differences are present as shown in Figure 4.3. The pins TS and GND are not connected since the voltage connected to TS will not reach above 100V, therefore that extra circuitry becomes redundant. By separat- ing the pins there is no need for a signal transformer and signal OutB and OutD from LTC3722-1 can be directly connected to LTC4440s Input pin. Otherwise, the principle is identical to the setup for signals A and C. This implementation in the complete circuit is marked with "B" in Figure 4.1. The results of the physical implementation of the gate driver is displayed in figures 4.4 to 4.6 below where the gate-source voltage is presented, before and after the gate driver circuit. From the figure it is observable that the gate source voltage is delayed compared to the signal emitted from the driver circuit LTC3722-1. The gate source voltage reaches close to 12 Volts but due to the diodes D1 and D11 in Figure 4.2 and 4.3 there is a small voltage drop due to the forward voltage of the diodes. 40 4. Results Figure 4.3: Circuit design for implementation of LTC4440 mattering MOSFETs Q2 and Q4. 0 0.5 1 1.5 2 2.5 3 Time [ s] 0 3 6 9 12 V o lt a g e [ V ] Figure 4.4: Measured input and output voltage of the primary side gate drivers. Input gate driver = B & Gate source voltage = VGS for Q2 in Figure 4.3. The delay present in Figure 4.4 is of importance since it affects the tuning of the switching signals and needs to be considered in order to achieve ZVS. Further vi- sualisation of the delay imposed by the gate driver is presented in Figures 4.5 and 4.6. The turn on delay is determined by the time differnace between the two signals at the point where they have reached 50% of its expected voltage amplitude. With this definition the turn on delay is determined to 41 ns. 41 4. Results 0 0.05 0.1 0.15 0.2 0.25 0.3 Time [ s] 0 3 6 9 12 V o lt a g e [ V ] Figure 4.5: Measured turn on delay on the primary side gate drivers. The turn off delay is determined using the same definition as for the turn on delay, where it is determined to 42ns. Both the turn on and off delays are presented in the data sheet of the driver circuit to be 30 and 28 ns, that delay correlates to driving a MOSFET with input capacitance of 1000 pF [41]. The MOSFETs used in this circuit, which are presented in Figure 4.1, has an input capacitance of approximately 2300 pF, resulting in an increased delay compared to the one offered in the data sheet. 0 0.05 0.1 0.15 0.2 Time [ s] 0 3 6 9 12 V o lt a g e [ V ] Figure 4.6: Measured turn off delay on the primary side gate drivers. 4.1.3 Secondary side design 4.1.3.1 MOSFET gate driver As mentioned in chapter 2.5.2, the resistors R13 to R18 are crucial for negative current protection provided by the gate driver LTC3901, where the calculated values using (2.7) to (2.10) can be found in Appendix A.1. Furthermore, the gate signals 42 4. Results OutE and OutF from LTC3722-1 will be connected to the gate driver through a signal transformer in order to keep the isolation between the primary and secondary side of the circuit, see T4 in Figure 4.7. Figure 4.7: Circuit design for implementation of LTC3901. 43 4. Results One way to power the gate driver through pin PVCC is using the design consisting of Q21, R19 and D17 combined with the output voltage. This design will ramp up the input voltage to 10 V in accordance with the output voltage, which provides a soft start and removes the requirement of an external power source. The components C7 to C10 and R20 to R22 are determined using standard values provided from the data sheet of the driver circuit LTC3901 [17]. Those components are mainly used for signal filtering and tuning for LTC3901. The implementation of this gate driver is marked with "C" in Figure 4.1. However, just as in the case of the primary side gate driver, using a secondary side gate driver will generate delays. Further delays will also be present due to the signal transformer T4 in Figure 4.1. The delay of the gate signal is presented in Figure 4.8, where a more detailed image of the turn-on and off delay is observable in Figures 4.9 and 4.10. The turn on delay was determined in the same manner as for the primary gate drivers and was determined to be 50 ns whilst the turn off delay was determined to 42 ns. The delay presented in the data sheet for the LTC3901 circuit was 60 ns when using a MOSFET with an input capacitance of 4700 pF [17]. When the gate driver operates in this circuit, powering MOSFETs Q5 to Q12 in Figure 4.1, each equivalent input capacitance is 4500 pF, resulting in less delay than what was presented in the data sheet. 0 0.5 1 1.5 2 2.5 3 Time [ s] 0 3 6 9 12 15 V o lt a g e [ V ] Primary driver Gate source voltage Figure 4.8: Measured input and output voltage of the secondary side gate driver. Primary driver = F & Gate source voltage = MF in Figure 4.7. 44 4. Results 0 0.05 0.1 0.15 0.2 Time [ s] 0 3 6 9 12 15 V o lt a g e [ V ] Primary driver Gate source voltage Figure 4.9: Zoomed in turn on delay for secondary side MOSFETs from Figure 4.8. 0 0.05 0.1 0.15 Time [ s] 0 3 6 9 12 V o lt a g e [ V ] Primary driver Gate source voltage Figure 4.10: Zoomed in turn off delay for secondary side MOSFETs from Figure 4.8. 4.1.3.2 Snubber design To ensure limited oscillations due to the hard-switching MOSFETs on the secondary side of the converter, the snubber block "F" in figure 4.1 was implemented. It consists of two RCD snubbers, since the full bridge switches polarity and therefore requires protection against both positive and negative voltage transients. It was decided to implement the snubber on the primary side of the transformer since then the positive over-voltage protection snubber was able to be connected to Vin, setting the lowest threshold of the snubber operation to only occur when surpassing the input voltage. This would not be possible if located on the secondary side since the positive voltage amplitude over the secondary side transformer will always be approximately two times larger than the output voltage, leading to a constant damping of the positive voltage to half the expected voltage magnitude. Therefore, to ensure correct operation the RCD snubber is located on the primary side. 4.1.3.3 LC-filter and bulk cap selection The output capacitor, inductors LS1 and LS2 according to Figure 2.11 are designed using the specifications listed in Table 4.1 combined with (2.17) to (2.22). The design parameters are presented in Table 4.2. 45 4. Results Table 4.1: Reference values used for determining the output inductor and capacitor. Value Unit Vout 56 V ∆Vout 1 % Pout.min 400 W Pout.max 1200 W T 5 µs Table 4.2: Calculated values for the inductors and the bulk capacitor. Value Unit Iout 7.14-21.43 A ILS 3.57-10.71 A ∆ILS.pp 7.14 A LS 28.22 µH ∆ICout 4.37 A Rc 128 mΩ The implementation of the LC-filter in the complete circuit is marked with "D" in Figure 4.1. 4.1.4 Transformer Selection and design The use of a current doubler simplifies the secondary side of the transformer, since there is only one secondary side winding used. The turn ratio for a current doubler can thus be determined from (2.11) where Vin(min) and Vout are from the converter specification set to 350 V for the input voltage and 56 V on the output. The maximum allowable duty cycle was set to 0.9. The maximum allowable turn ratio was then determined to 2.8. Since the turn ratio needs to be fractions between even number of turns for both primary and secondary side the turn ratio was selected to 2 which will also give some headroom for the duty cycle. The oscillator frequency was set to 400 kHz, and the transformer will experience half of the oscillator frequency. The high switching frequency means that material selection is important. Due to Eddy currents the most suitable material for the core is ferrite. A comparison between different sized ferrite cores allows the possibility to compare which core are suitable set for different number of turns in terms of peak flux density which is presented in Table 4.3. 46 4. Results Table 4.3: Peak flux density for different ferrite cores for different number of primary turns. Np E100/60/28 E65/32/27 ETD59/31/22 E42/21/20 Magnetic Flux density [mT] 2 612 841 1222 1923 4 306 420 611 961 6 204 280 407 640 8 153 210 305 480 10 125 168 245 385 12 102 140 203 320 14 87 120 175 275 16 76 105 153 240 18 68 93 136 214 20 61 84 122 192 The flux densities calculated in Table 4.3 is calculated from (2.13) using the nominal input voltage of 400 V, a maximum duty cycle of 0.9 and a time period of 5 µs which corresponds to the transformer switching frequency of 200 kHz. From Table 4.3, a higher turn ratio yields lower flux peaks which in turn will yield lower core losses. The ferrite material also saturates at 300 mT and thus eliminates the use of most of the low number of primary turns from all cores. In the end the core E65/32/27 from TDK was selected since it has a rather large effective area and a large window area for the windings. The E100/60/28 yields a lower flux density, but the overall size of the core is much larger and would increase the overall size of the converter significantly and the core losses are only slightly reduced. To achieve a low flux swing in the transformer, 18 turns was wound on the primary to have a low flux swing while still ensure enough space to fit the windings in the window area. The layout through the sectional window area of the transformer was determined according to Figure 4.11. 47 4. Results Isolation layer Primary turn Secondary turn Space for isolation Magnetic core Figure 4.11: Cross-sectional transformer winding. The layout of the windings was chosen to keep the winding procedure manageable, by alternating windings the leakage inductance would decrease further, but at the cost of increased complexity of the winding procedure. Since a larger leakage inductance would improve ZVS, the layout consists of all the primary wires close to the core and secondary wires on top of the primary windings. Both primary and secondary side windings consist of litz wire to counteract increased resistances due to skin effect. The skin depth for a round copper conductor at 200 kHz was determined using (2.16), and is 0.145 mm. The litz used consists of multiple 0.1 mm diameter copper wires. Since the skin depth is larger than the diameter of the wire the skin effect will not increase the overall winding resistance. The total amount of copper area seen placed into the window area is 68 mm2 for the primary side and 78 mm2 for the secondary side. The core has a window area of 562 mm2 which gives an ideal copper fill factor of 0.28. The low fill factor is just for the conducting wires, isolation tape and the fact that the wired does not ideally fill up the window area will yield in a fill factor that is close to 1 and thus fills up almost the whole window area. 48 4. Results 4.1.4.1 Transformer parameters The transformer parameters are displayed in Figure 2.18, where the winding resis- tance R1 and R2 were measured with a four-pole resistance measurement. Llk1 was determined by short circuiting the secondary side of the transformer whilst measur- ing the inductance with an LCR-meter. The measurement of Llk2 was done in a similar manner but for the secondary side with a short circuited primary winding. Lm was measured with an LCR-meter on the primary side whilst the secondary side was an open circuit. The resulting values from the measurements are displayed in the Table below. Table 4.4: Resulting Transformer parameters. Value Unit R1 12 mW R2 7 mW Llk1 5 µH Llk2 1.6 µH Lm 2.5 mH 4.1.4.2 Transformer loss estimation Core losses are based on the peak flux density and for the E65/32/27 with 18 primary turns results in a flux density of 93 mT. From the datasheet of the core material, the relative core losses per core volume for a frequency of 200 kHz and a flux swing of 93 mT can be estimated, multiplying with the total volume of the core results in the core losses. The 93 mT flux swing is a worst-case scenario, where the duty cycle is maxed out at 400 V at the input, in steady state the duty cycle will be lower which will decrease the voltage-second product in (2.13) and thus decrease the flux swing and peak flux density. The voltage-second product can be determined from the numerator in (2.13) and is summarised from different scenarios together with the core losses in Table 4.5 below. The duty cycle used can be determined from rearranging (2.11). 49 4. Results Table 4.5: Resulting magnetic properties and core losses for different scenarios and temperatures at max power. Scenario Load= 1.2 kW Voltage-second [mWb] Flux density [mT] Core losses [W] Maxed duty Vin=400 V D=0.9 1.80 93 100 °C 13.8 25 °C 23.6 Maxed duty Vin=350 V D=0.9 1.58 82 100 °C 11.2 25 °C 17.5 Steady state Vin=400 V D=0.56 0.56 60 100 °C 6.2 25 °C 7.9 Steady state Vin=350 V D=0.64 0.56 60 100 °C 6.2 25 °C 7.9 At steady state core losses are reduced compared to when the converter is operating at its limits. The core material also operates more efficiently for core temperatures above ambient temperature. Copper losses for the circuit can be estimated using (2.14) where the resistance for ambient temperature copper windings is presented in Table 4.4. By using the simulated current values, it is possible to estimate copper losses. Primary side copper losses can be estimated to 0.77 W for an input voltage of 350 V and a max output power. Whilst the secondary side copper losses are estimated to 1.8 W. 4.1.5 Zero voltage switching capabilities With the primary MOSFETs having a parasitic output capacitance of 111 pF to- gether with the sum of leakage inductance and primary inductance of 8.3 µH the ZVS minimum load condition can be determined according to (2.4). The input volt- age will determine the minimum load to achieve ZVS. A higher input voltage would result in a lower current for a given load. The resulting minimum power required to achieve ZVS is displayed in the Table below for the upper and lower voltage limit. Table 4.6: Lowest possible input power in order to achieve Zero voltage switching. Input voltage (V) Input current (A) Input power (W) 350 2.1 731.5 400 2.38 955.5 50 4. Results 4.1.6 Feedback circuit design The feedback circuit has been designed as displayed in Figure 4.12 which corresponds to section E for the final circuit design in Figure 4.1. LT1431 is used and corresponds to the error amplifier in Figure 2.22 and works as a shunt voltage regulator. By regulating the voltage seen on the Collector pin (Coll) the circuit can regulate the voltage over the optocoupler MOC207. The optocoupler provides galvanic isolation between the primary and secondary side and based on the current flowing through the optocoupler diode the voltage over the comparator pin on LTC3722-1 will be determined, resulting in PWM modulation. Zener diode D18 and resistance R43 acts as a voltage divider where the breakdown voltage of the Zener diode is used to keep the voltage constant independent of the output voltage. All excess current will flow through the diode keeping the voltage constant over the optocoupler. Figure 4.12: Circuit design for implementation of the feedback system. Resistors R44 to R47 and capacitors C11 and C12 corresponds to the components of the Type III regulator seen in Figure 2.22. But in order to select the components the circuit the behaviour of the converter must firstly be determined. By using (2.23)-(2.25) with the parameters displayed in the Table below, the Bode plot of the converter can be determined. 51 4. Results Table 4.7: Values used for the phase shifted full bridge transfer function. Value Unit Rload 2.6 W Vin 400 V N 2 L 15 µH Cout 1350 µF Rc 8.8 mW R1 0.61 W R2 2.61 W The resulting Bode plot of the converter thus become 10 1 10 2 10 3 10 4 10 5 10 6 -40 -30 -20 -10 0 10 20 30 40 50 Figure 4.13: Bode gain plot of converter behaviour. 10 1 10 2 10 3 10 4 10 5 10 6 -135 -90 -45 0 Figure 4.14: Bode phase plot of converter behaviour. from Figure 4.13, the PSFB will amplify low frequency content and attenuate all fre- quencies above the crossover frequency which is around 20 kHz. The gain crossover frequency should however be placed before the zero created by the output filter of the converter which is placed at around 14 kHz. The behaviour of the converter is modified by the implementation of the Type III regulator in Figure 2.22. By plac- ing the poles and zeros of the compensator network the phase margin which is seen in Figure 4.14 can be kept stable. The phase margin is around 60 degrees for the converter. The components used in the Type III regulator are presented in Table 4.8 and are referenced to the notations used in Figure 2.22 and 4.12. 52 4. Results Table 4.8: Values used for Type III regulator. Name used in Type III Name in Circuit Value R1 R44 82 kW R2 R45 82 kW R3 R47 3838 W R4 R46 100 kW C1 C11 1 nF C2 C12 100 nF C3 - - With the selected values, the poles and Zeros can be calculated using (2.26)-(2.30) and are presented in Table 4.9. Table 4.9: Zeros and poles for the compensator network. Frequency [Hz] fz1 970 fz2 200 fp0 15 fp1 1940 fp2 - The pole fp2 is neglected due to not using the capacitance. A small would place the pole at high frequencies where the converter would already attenuate the signal. The poles and zeros of Table 4.9 generates the following transfer function behaviour 10 1 10 2 10 3 10 4 10 5 -25 -20 -15 -10 -5 0 5 Figure 4.15: Bode gain plot of converter behaviour. 10 1 10 2 10 3 10 4 10 5 -90 -45 0 45 Figure 4.16: Bode phase plot of converter behaviour. by placing a pole at low frequency as seen in Figure 4.15 the converter speed can be decreased in order to place the crossover frequency below the zero created by 53 4. Results the output capacitor. The phase response seen in Figure 4.16 ensures that the phase margin of the converter is not decreased by the compensator. Combining the converter and compensator behaviour will give the overall system behaviour which is displayed below. 10 1 10 2 10 3 10 4 10 5 -40 -30 -20 -10 0 10 20 30 40 50 Figure 4.17: Bode gain plot of converter behaviour. 10 1 10 2 10 3 10 4 10 5 -150 -120 -90 -60 -30 Figure 4.18: Bode phase plot of converter behaviour. The overall converter can be observed in Figure 4.17 and 4.18 where the converter will have a crossover frequency close to 5 kHz and thus a margin of 9 kHz to the converter zero created by the output filter. The phase margin remains at 60 degrees. 4.1.7 Driver circuit setup The section covers how LTC3722-1 and corresponding features are implemented. The components presented below can be seen in Figure 4.1 and their specific values are listed in Appendix A.1. The converter was decided to be designed for a switching frequency of 200 kHz, re- sulting in a required 400 kHz oscillator frequency. In this case the internal oscillator is used since it will not be coupled in parallel with other converters. The frequency is set by selecting the value of capacitor C17 according to data sheet of the driver circuit. A soft-start for the converter is implemented to slowly ramp up the converter oper- ation in order to limit large current spikes during start up. The soft start feature is implemented using a capacitor which is slowly charged which will determine the soft start duration. In this case a resistor in series is also used to allow for a small DC offset when starting the circuit. Two diodes are also placed in opposite directions to allow for fast discharging of the capacitor if the circuit need to recommence a soft start. The soft start setup can be seen in Figure 4.19 where its implementation is used in the final design according to Figure 4.1. 54 4. Results Figure 4.19: Circuit design for implementation of the soft start. The current sense of the PSFB measures the primary