Combined onboard charger and DC-DC
converter design
in a Plug-in Hybrid Vehicle
Master’s Thesis in Electrical Power Engineering

Mingzhi Xue
Jiaao Tong

Department of Electric Engineering
CHALMERS UNIVERSITY OF TECHNOLOGY
Gothenburg, Sweden 2018





MASTER’S THESIS 2018:NN

Combined onboard charger and DC-DC converter design
in a Plug-in Hybrid Vehicle

MINGZHI XUE
JIAAO TONG

Department of Electric Engineering
Division of Electric Power Engineering

CHALMERS UNIVERSITY OF TECHNOLOGY

Gothenburg, Sweden 2018



Combined onboard charger and DC-DC converter design
in a Plug-in Hybrid Vehicle
Mingzhi Xue
Jiaao Tong

© Mingzhi Xue & Jiaao Tong, 2018.

Supervisor: Sven Sjöberg, CEVT
Examiner: Torbjörn Thiringer, Department of Electric Engineering, Chalmers

Master’s Thesis 2018:NN
Department of Electric Engineering
Division of Electrical Power Engineering
Chalmers University of Technology
SE-412 96 Gothenburg

Typeset in LATEX
Printed by [Chalmers University of Technology]
Gothenburg, Sweden 2018



Combined onboard charger and DC-DC converter design in a plug-in hybrid vehicle
Mingzhi Xue and Jiaao Tong
Department of Electric Engineering
Chalmers University of Technology

Abstract

To enhance the power density by reducing the charging system’s volume, this master thesis
designed and optimized a combined onboard charger and DC-DC converter with a three-
winding transformer for a plug-in hybrid vehicle platform.

The topology adopts a dual active full bridge (DAB) design as the DC-DC isolated converter
in the OBC and a full-bridge DC-DC converter with current doubler and synchronous rec-
tification for the 12V battery charging. In the project, these two different typologies were
investigated and simulated in LTspice. Zero Voltage Switching (ZVS) has been implemented
and its operation has been verified in order to decrease the switching losses. A three-port high
frequency transformer is designed to keep a high power density. Power losses and efficiency
are calculated and presented in this report. Moreover, the real component selection and the
comparison related to efficiency, volume and cost are made between the new design topology
with a three-port HF transformer and the existing conventional charging system.

The simulation, power losses and efficiency are analyzed of the nominal operating point
in this project. The simulation result shows that the ZVS strategy is achieved successfully
for efficiency improvement. The volume of the transformer has been minimized with the
appropriate design of the core and windings. The power losses includes switching loss,
conduction loss, core loss and copper loss in the transformer. For the DC/DC converter in
the OBC, the efficiency can reach 94.8% at the nominal operating point and regarding the
full-bridge DC/DC converter, the efficiency can reach 93.57% at the nominal operationg
point. Compared with the single packages for the OBC and DC-DC component, the price
saved is roughly about 613 Sek and the dimension saved is approximately 72 cm3.

Keywords: On board charger, DC-DC converter, three winding transformer, plug-in hybrid
vehicle.

v





Acknowledgements

We would like to express our sincere gratitude to our supervisor Sven Sjöberg at CEVT for
providing us the opportunity to perform this project. Furthermore, we would like thank all
the people who helped and supported us during the project, especially to Sepideh Amirpour
for the useful comments and supports.

We are especially indebted to our examiner Prof.Torbjörn Thiringer for his immense help
and insightful comments. His guidance helped us a lot and direct us reaching the goals.

Last but not least, we are grateful to our parents for supporting us throughout all our studies
at Chalmers. Their love and guidance are with us in whatever we pursue.

Mingzhi Xue and Jiaao Tong, Gothenburg, 2018

vii





Table of Contents

Abstract v

Acknowledgements vii

Abbreviations xi

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Sustainability and ethics aspects . . . . . . . . . . . . . . . . . . . . . . . 3

2 Theory 5
2.1 Design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Soft switching - Zero Voltage Switching . . . . . . . . . . . . . . . . . . . 5
2.3 DC-DC part of OBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3.1 Switching pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.2 Circuit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 DC-DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 DC-Dc switching pattern . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Circuit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 Semiconductor losses determination . . . . . . . . . . . . . . . . . . . . . 23

2.6.1 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.2 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.7 Topology overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Case set up 27
3.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Passive components selection . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.1 DC-DC part of OBC resonance inductance selection . . . . . . . . 28
3.2.2 DC-DC Passive components selection . . . . . . . . . . . . . . . . 29

3.3 Operation frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4.1 Semiconductor selection . . . . . . . . . . . . . . . . . . . . . . . 30
3.5 Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ix



Table of Contents

3.5.1 Turns ratio determination . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.2 Core Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.3 Winding Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Results and analysis 35
4.1 Topology simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.1 OBC charging path simulation and analysis . . . . . . . . . . . . . 36
4.1.2 DC-DC topology simulation and analysis . . . . . . . . . . . . . . 40

4.2 Transformer selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.1 Turns determination . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.2 Core design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2.2.1 OBC isolated transformer . . . . . . . . . . . . . . . . . 46
4.2.2.2 DC-DC isolated transformer . . . . . . . . . . . . . . . . 48
4.2.2.3 Three winding transformer . . . . . . . . . . . . . . . . 50

4.2.3 Winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.3.1 OBC transformer . . . . . . . . . . . . . . . . . . . . . 52
4.2.3.2 DC-DC transformer . . . . . . . . . . . . . . . . . . . . 52
4.2.3.3 Three winding transformer . . . . . . . . . . . . . . . . 52

4.3 Semiconductor losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3.1 Semiconductor losses for OBC . . . . . . . . . . . . . . . . . . . . 54
4.3.2 Semiconductor losses for DC-DC . . . . . . . . . . . . . . . . . . 58

4.3.2.1 DcDc full bridge topology semiconductor losses . . . . . 58
4.3.2.2 DC-DC current doubler topology semiconductor losses . 58

4.4 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4.1 Efficiency of OBC path . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4.2 Efficiency of DC-DC path . . . . . . . . . . . . . . . . . . . . . . 61

4.5 Design comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Conclusion 63
5.1 Results from present work . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

References 65

x



Abbreviations

AC Alternating Current

DAB Dual active full bridge

DC Direct Current

DC-DC DC to DC Converter

HF High frequency

HV High Voltage

OBC Onboard Charger

RMS Root Mean Square

ZVS Zero Voltage Switching

xi





1
Introduction

1.1 Background

The ever more pressing topic of exhaust gas emission reductions leads the automotive indus-
try to develop more environment friendly technologies. Besides, the fact that fossil fuels are
being depleting also encourages the development of sustainable transportation. Hence, vehi-
cle manufacturers intend to integrate hybrid power trains in conventional vehicles, and even
to replace it with fully electrical ones. In addition, the hybrid vehicle has a higher efficiency
and the possibility to regenerate the kinetic power to electric power for later use, which also
makes the hybrid vehicle quite popular with customers.

Based on customer requirements and market expectations, a better performance and still a
low cost hybrid vehicle is a logical step .The hybrid propulsion system is based on a complex
systems of power electronic devices. Furthermore, the concept of power density of power
electronic converters is most widely utilized to present and evaluate the performance. There-
fore, the automotive industry requires a high power density of the power electronics as well
as a low cost.

The converter volume has a significant impact on the power density. Besides, a small vol-
ume requirement allows a greater design freedom and a lower capital outlay in the building
infrastructure[1]. Hence, it is accordingly necessary to think about package volume reduc-
tion.

There are several different charging system typologies that are known today. One common
design is shown in Figure.1.1. It is indicated that that the onboard charger(OBC) and DC/DC
converter are packaged separately. The OBC package is designed as the AC/DC together
with a DC/DC converter to charge the high voltage batteries. The isolated buck DC-DC
converter is designed in another package, which is fed by the battery and supplies the 12V
power net needed for auxiliary purposes in a hybrid electric vehicle. The transformer for
galvanic insulation is applied in both the OBC charger and DC/DC converter, which takes
much space due to the usages of two packages. Therefore, one can consider to combine these
two packages into a compact one and a three winding transformer will be used to transfer
power, shown in Figure1.2. Consequently, the volume of the power electronic device has a
potential to be lower due to the new combined transformer as well as the sharing of cooling
system. In this thesis work, this thought will be discussed and the performance will be
evaluated.

1



Chapter 1. Introduction

Figure 1.1: The existing architecture of the charging system with an extra 12V storage system.

Figure 1.2: Design Overview.

1.2 Previous work

The previous work [5] investigated the full bridge with full wave rectification and full bridge
with current synchronous rectification regarding ZVS implementation, transformer design
and power losses calculation. The result shows the feasibility to investigate further for charg-
ing system in hybrid vehicle. Therefore, based on the previous work, a dual active bridge
for the DC/DC part of OBC and a full-bridge DC-DC converter with current doubler and
synchronous rectification for charging 12V power-net are investigated as well as a proper
three-winding transformer design is implemented so as to achieve high power density for the
charging system.

1.3 Purpose

The main objective of the thesis work is to design a combined on board charger and DCDC
converter through using three-winding transformer for a plug-in hybrid vehicle to increase

2



1.4 Sustainability and ethics aspects

the power density compared with the conventional topology. In order to integrate the system
and keep high efficiency, the focus is on the converter topology and using a three-port HF
transformer instead of two conventional transformers.

1.4 Sustainability and ethics aspects

We hereby declare the thesis work is carried out by ourselves under the guidance of our
supervisor and examiner. The content, data and result are authentic, which is obtained by
the logical and valid derivation and quotation. Efforts have been made to describe the work
carefully so that it can be reproduced by readers.

The outcome of the project is targeted for hybrid and electrical automotive industry which
is aiming to reduce air pollution. The thesis outcome reduces the existing design cost and
losses and contributes to the product environmental friendly and sustainable development.
We did not choose any component which includes non-desirable material and will not cause
misery on earth.

3





2
Theory

2.1 Design overview

PHEVs charging system consists of an OBC for high voltage battery system and a DC-DC
converter for low power system. In order to increase the power density and save space,
the OBC could be combined with the DC-DC converter through an isolated three-winding
transformer.

In normal case the OBC includes AC/DC boosting converter with PFC and DC-DC converter
for high voltage battery system. In this design, the concentration will be the OBC DC-DC
isolated converter combined with the 400-12V DC/DC converter for low power system.

As Figure1.2 shown ,there are two power flow paths, which is conducted by different typolo-
gies. Hence, these two typologies will be discussed separately.

2.2 Soft switching - Zero Voltage Switching

In all the pulse-width-modulated dc-to-dc and dc-to-ac converter typologies, the controllable
switches are operated in a high frequency switch mode where they are required to turn on
and turn off the entire load current during each switching. In such a switch-mode operation,
the switches are subjected to high switching stresses and high switching power losses that
increases linearly with the switching frequency. Another significant drawback of the switch-
mode operation is the EMI produced due to large di/dt and dv/dt caused by a switch-mode
operation[6]. However, in order to reduce the size and volume of the converter and hence to
increase the power density, the high switching frequency operation mode is unavoidable.

Therefore, one can reduce the switching losses by turning on and off each converter MOS-
FET when either the switch voltage or current is zero. Ideally, if each switch changes its
status when the voltage across it is zero, this will result in zero-voltage switching(ZVS)[6].
Consequently, the switching losses will be reduced largely. With the help of the MOSFET’s
junction capacitance and the reverse recovery diode, ZVS can be achieved in this master the-
sis work. It eliminates the switching loss as well as di/dt noise, which enables the converter
to operate at a high switching frequency.

5



Chapter 2. Theory

2.3 DC-DC part of OBC

The dual active bridge(DAB) is commonly proposed for HV applications in this research
field. Its character is bidirectional power transfer, which is very suitable for high voltage
battery charging system fed by a battery in driving mode. Besides, a high frequency isolated
transformer is involved in the DAB, which can provide the isolation for safety as a charger
in hybrid/electric vehicles. The topology of a dual active bridge is shown in Figure 2.1.

The converter consists of eight active switches which are placed on four legs as full bridge
structures and a HF transformer. Four switches are located on the primary side and the other
four are placed on the secondary side. Both sides are isolated by a HF transformer. Since the
leakage inductance of the transformer and the parasitic capacitance of the active components
can be utilized to achieve the ZVS soft switching technology with the combination of a
proper converter topology and a suitable switching pattern. This can be utilized to minimize
switching losses, which, in return, will increase the switching frequency and subsequently a
reduce size and weight of the transformers and the passive components numbers.

The main merit of the DAB are the low number of passive components, the evenly shared
currents in the switches, its soft switching properties and flexible control strategy. With the
DAB converter topology, high power density is possible. [2][3]

2.3.1 Switching pattern

Figure 2.1: Dual active bridge topology schematic.

6



2.3 DC-DC part of OBC

Figure 2.2: Simplified DAB circuit.

Redrawing the DAB converter as shown in Fig.3.1 and from the simplified schematic Fig.3.2
shown above, according to suitable control of the switches, two square voltage waves can be
achieved on both sides of the transformer, VAB and VCD. V ′CD is the transferred voltage from
the secondary side to the primary side. Energy passes through the inductance L between the
two sources. Flexible control strategy can be achieved by adjusting the duty cycle of VAB,
the duty cycle of V ′CD and phase shift angle between VAB and V ′CD. In this case, we define
the voltage ratio k = KV2/V1. When k 6 1, the converter transfers positive power but the
converter transfers negative power when k > 1. For a charging system, k 6 1 is applied for
the positive power transfer. Dφ is defined as the duty cycle corresponding to the phase shift
between VAB and VCD, while Dy1 is the duty cycle of VAB.

The most commonly used modulation method, phase shift modulation, operates the DAB
with a constant frequency and with maximum duty cycles. The two switches in every arm
just conduct 180°complementary and the diagonal switches keep on and off action simul-
taneously. It solely changes the phase shift angle to control the transferred power[8]. The
main advantage of this pattern is its simplicity as only one variable need to be controlled. Ba-
sic on the phase shift switching modulation, adding another controllable variable, the duty
cycle of the primary side. Considering this pattern, the two switches in every arm conduct
180°complementary. The two legs of the primary side adopt the phase shift pattern which
means Q1 and Q2 leading Q3 and Q4. The duty cycle of the primary voltage VAB can be
controlled through the phase shift of this two arms. The diagonal switches on the secondary
side turns on or off simultaneously. Consequently, the transferred power are adjusted using
the phase shift angle between VAB and VCD. The great merits of this switching modulation are
a wide range of soft switching and a smaller RMS currents using high frequency transformer
compared with the phase shift modulation.[11]

7



Chapter 2. Theory

2.3.2 Circuit operation

Figure 2.3: Gate signals and main waveforms of the DAB converter.

Figure 2.3 shows the gate control signals and main waveforms of a dual active full bridge
converter. The operation of the DAB converter with ZVS in different time periods are shown
from Figure 2.4 to Figure 2.8. The operation of the circuit is achieved by a proper turn on/off
sequence of eight switches (Q1 to Q8). Moreover, there are an anti-parallel body diode and
an output parasitic capacitance embedded inside the MOSFET which can realize the ZVS
operation in consideration with the inductance. And the inductance is the sum of the leakage
inductance and a passive external inductance.

Considering the blanking time between the upper and lower switches in each leg, which
avoid short circuit and provide the time interval for ZVS operation, the duty cycle is slightly
less than 50% for each switch. The converter operation is explained at the following part.

8



2.3 DC-DC part of OBC

During a half switching cycle [t0, t4], there are four switching instants that are shown from
Figure 2.4 to Figure 2.8. Since the switching process is very short, the transient process is
neglected to simplify the analysis.

Mode I: Initial condition t0

Suppose that Q1 and Q3 are conducting before time instant t0. The primary side current is
negative flowing D1 and Q3. And the current in secondary side goes through D6 and D7. In
this mode, the inductance L releases energy to the voltage source V2. This process can be
seen from Figure 2.4.

Figure 2.4: Operation of the DAB converter with ZVS at time t0.

Mode II: Start of the right leg transition in primary side [t0, t1]

Q3 is turned off at time instant t0, C3 is charged by iL while C4 is discharged. Due to the
capacitance C3 and C4, Q3 can be switched off with zero voltage. When the voltage of C3
reaches V1 and the voltage of C4 decreases to zero, the body diode of Q4 , D4, will conduct
naturally to turn on Q4 with zero voltage. Now, VAB =V1, VCD =−V2 and VL =V1+KV2, so
iL increases with the slope

diL
dt

=
V1 +KV2

L
(2.1)

At time instant t1, iL increases from minus to zero, meanwhile D1, D4, D6 and D7 will be
turned off naturally.

9



Chapter 2. Theory

Figure 2.5: Operation of the DAB converter with ZVS at [t0, t1].

Mode III: Completion of the right leg transition in primary side [t1, t2]

At time instant t1, iL becomes positive flowing through Q1 and Q4, so VAB = V1. Then the
secondary side current runs through Q6 and Q7, which means VCD =−V2. So VL =V1+KV2
at this moment, iL keeps increasing. In this mode, the power source V1 and V2 supply the
energy to the inductance simultaneously.

Figure 2.6: Operation of the DAB converter with ZVS at [t1, t2].

Mode IV: Switching commutation in secondary side [t2, t3]

The switches Q6 and Q7 are turned off at t2 and C6 and C7 are charged by iL. At the same
time, C5 and C8 are fully discharged. Because the voltage between the capacitance can not
change instantly, Q6 and Q7 achieve turn off with zero voltage. When C6 and C7 are fully
charged, which means the voltage of C5 and C8 reach zero. Then the anti-parallel diode will
conduct automatically. Hence, Q5 and Q8 will be turned on with zero voltage. Meanwhile,
VAB = V1, VCD = V2 and VL = V1−KV2. iL still keeps increasing, but the increasing slop
changes to

10



2.3 DC-DC part of OBC

diL
dt

=
V1−KV2

L
(2.2)

In this mode, the inductance L releases energy to the source V2.

Figure 2.7: Operation of the DAB converter with ZVS at [t2, t3].

Mode V: Start of the left transition in primary side [t3, t4]

Q1 is turned off at time t3, C1 is charged by iL and C2 is discharged. At this moment, Q1
can realize zero voltage turned-off. Once the voltage of C1 increases to V1 and C2 is fully
discharged, the anti-parallel diode of Q2 will conduct and Q2 can be turned on with zero
voltage. Now VAB = 0,VCD =V2, but iL begins to decrease with a negative slop:

diL
dt

=
−KV2

L
(2.3)

After time instant t4, the DAB converter will start to operate in another half circle, which is
the similar operation explained above.

Figure 2.8: Operation of the DAB converter with ZVS at [t3, t4].

11



Chapter 2. Theory

Based on Fig2.3, the inductance current in one half cycle can be induced when t0≤t<t2

i(t) =
(1+ k)V1

L
(t− t0)−

(Dy1 + kDy1 +2kDφ −2k)V1

4L fs
(2.4)

When t2≤t<t3, the inductance current can be calculated as

i(t) =
(1− k)V1

L
(t− t2)−

(k+2kDφ −1)V1

4L fs
(2.5)

While t3≤t<t4, the expression of the inductance current becomes:

i(t) =
−kV1

L
(t− t3)+

(Dy1− kDy1 +2kDφ )V1

4L fs
(2.6)

According to the Fig2.3 and [11], the input average power can be described as

P =
kV 2

1
8L fs

[1− (1−2Dφ )
2− (1−Dy1)

2] (2.7)

The ability of power transfer is determined by Dφ and Dy1. The higher values of Dφ and
Dy1, the higher power can transfer. When Dφ =1 and Dy1=0.5, the converter transfers the
maximum power.

2.4 DC-DC

When the main 400V battery is going to charge the 13.8V Li-ion battery, the DC-DC will
work to bring the voltage down. In this project, the DC-DC is designed as a full-bridge
DC-DC converter with current doubler and synchronous rectification.

In this case, the secondary side of the dual active bridge, which is introduced in Section 2.3,
will act as the full-bridge converter on the input side. At the output side, there are different
available typologies that could be compared and selected from, full-wave and half full-wave
rectification, full bridge rectifier and current doubler rectifier, etc. They are all able to work
good for the scenario of low voltage and high current output. Among them, the current
doubler(Fig.2.9) topology is first introduced and selected.

12



2.4 DC-DC

Figure 2.9: The topology of current doubler.

Compared to the most common used centre tapped full wave rectifier, the secondary side
of the transformer only sees half of the output current with no center tapping needed. This
makes the transformer to achieve a higher efficiency as well as an optimized and simplified
structure. In contrast with the full wave rectifier, this structure only needs two diodes, not
four. Instead, two inductors are applied. Although the number of the output filter inductors
increases, it has a big advantage of reducing the size of each filter inductor[4][5]. In addition,
the output ripple current is added together by the two inductor currents, which has a small
current ripple as well as a fast response.

On the other hand, however, the diode voltage drops will be a high percentage of the output
voltage. The loss in the rectifier diodes is quite high and hence limits the efficiency. Instead,
synchronous rectification is a reasonable solution here. In terms of synchronous rectification,
the MOSFETs will replace and behave as the diodes. When there is a need to turn on or turn
off the diodes, the control signal SR1 and SR2 will be used to drive the MOSFET, which
will make it possible to make the MOSFETs to work as diodes and realize rectification. The
topology of a full bridge converter with a current doubler synchronous rectification of ideal
components is shown in Figure.2.10.

13



Chapter 2. Theory

Figure 2.10: The full-bridge DC-DC converter with current doubler and synchronous rectifier.

2.4.1 DC-Dc switching pattern

The switching pattern of phase shift modulation, introduced in Section 2.3.1, is also a perfect
widely used strategy to control the DC/DC converter. The switching pattern is shown in
Figure2.11. Signals of SA,SB,SC,SD are used to control the MOSFETs on the transformer
secondary side and SR1 as well as SR2 are the drive signal for the synchronous rectifier.

14



2.4 DC-DC

Figure 2.11: The switching pattern of Phase shift full bridge converter and current doubler.

For the DC-DC high voltage input side, the full bridge converter with phase shift strategy
leads an almost 50% fixed-duty cycle to the four MOSFETs. Beside, there is a phase shift
angle between the two leg driving signal, which is used to control the output voltage. There
is a small blanking time between A/B and C/D, shown as Delay A/B and Delay C/D in Fig-
ure2.11 . This is to prevent the MOSFETs on the same leg from turning on simultaneously,
which will lead to a short circuit and a destruction of the MOSFETs[7]. Besides, it will also
work enable Zero Voltage Switching.

The low voltage output voltage of this topology will act as a buck converter. The MOSFETs
will turn on and off to control the power transferred from the HV side. When the transfer
voltage VT is positive, Q1 is turned off and Q2 is on. When VT is negative, Q1 is on and Q2
is turned off.

In terms of ZVS, the transformer leakage inductance will work together with the MOSFETs
parasitic capacitance to realize soft switching of QA, QB, QC and QD. As the secondary
side, the filter inductance and the parasitic capacitance of synchronous rectifiers will achieve
ZVS.

15



Chapter 2. Theory

2.4.2 Circuit operation

The circuit operation can be divided into eight time intervals. The switching analysis of
the low power charging path will be discussed here following the control strategy shown
in Figure2.11. To be specific, the 400V is input of the secondary transformer winding and
13.8V is the output of the tertiary side. And only the secondary and tertiary windings of the
transformer will be described in the following schematics.

• Timeframe t0− t1

The first time interval operation schematic is shown in Fig.2.12.

At the beginning time t0 on the secondary side, QD has already turned on. The voltage
over MOSFET QA is zero and QA starts to turn on as well. Hence the secondary
current is flowing through Q1, transformer T1 side and QD. The power transfers from
the secondary side to tertiary side. VT is positive.

On the tertiary side, SR1 is off and SR2 is in on state. MOSFET Q2 will conduct
and take all the flowing current so no current will flows through MOSFET Q1. The
currents in L1 and L2 will flow in the same direction but two different paths. The
current flowing through L1 will keep increasing due to the force transformer voltage
VT. But L2 current will decrease with the freewheeling stored energy in L2.

Figure 2.12: Schematic operation at time interval t0− t1.

• Timeframe t1− t2

The operation schematic in this time interval is shown in Fig.2.13.

In this designed topology, there will be a resonant inductance Lr on the secondary
side, which results from the leakage inductance of the transformer. It will keep the
current in transformer secondary winding flowing in the same direction. At t1, QD is
turned off. The stored energy in resonant inductance will force transformer current
Ip to keep flowing of its value at t1. The current will start to discharge the MOSFET

16



2.4 DC-DC

output capacitance the COSS of QC and charge COSS of QD and as shown in Fig.2.13.
If Ip is adequate , the drain voltage of QD, and source voltage of QC, will resonate
from Vi,max to zero. When they reach zero, the current Ip stops flowing through the
COSS of QD. It turns on the body diode of QC and Ip keeps flowing[7].

Meanwhile on the tertiary side at the time instant t1, the forced voltage on the sec-
ondary side is off and transfers voltage changes from the maximum value to zero. In
this short time period, VDS of Q1 reaches zero voltage and the body diode of Q1 will
turn on. Since the secondary current Ip keeps almost the same value, the tertiary trans-
former side current will have almost the same value as at t1. Therefore, the current of
body diode Q1 will start at zero current and increase slowly. The diode current through
Q1 will continue to flow through L1 as the third path.

Figure 2.13: Schematic operation at time interval t1− t2.

• Timeframe t2− t3

The operation schematic in this time interval is shown in Fig.2.14

At t2, QA is still on and QC starts to turn on. The current still flows through QA,
however the current path through QC will changed form the the QC body diode to QC
MOSFET As shown on the secondary side, the current will flow by QA, T1, and QC.

On the tertiary side at time instant t2 , SR1 turns the MOSFET Q1 on. Since the body
diode of Q1 is already turned on, VDS of Q1 is zero. zero voltage switching will be
achieved during this turn on period. The third charging path will change from flowing
through the Q1 body diode to the MOSFET Q1 instead. The other two charging path
will be exactly the same within the timeframe t1− t2.

17



Chapter 2. Theory

Figure 2.14: Schematic operation at time interval t2− t3.

• Timeframe t3− t4

The operation schematic in this time interval is shown in Fig.2.15

At time t3, QA turns off. Similarly as in time period t1− t2, the stored energy in the
leakage inductance Lr will force Ip to keep flowing with its value at t3, which will
charge QA COSS however discharge QB COSS as shown in Fig.2.15. If Ip is adequate,
the QA source voltage will resonate from Vi,max to zero. The ZVS transition will
finish. After the QB drain voltage reach Vi,max, the current Ip stops flowing through
the COSS. Instead the current turns into the QB body diode on and keeps flowing.

At t3 with ZVS, the QA source voltage is resonated from the maximum to zero voltage.
In this period, the QB VDS reaches to value zero therefore the body diode is turned on.
The secondary current Ip still keeps the similar value, hence tertiary side current is
almost the same as the current value at t1. Therefore, the current of the body diode
Q2 will take all the current flowing the MOSFET Q2 at t3. The current path through
MOSFET Q2 is shifted to the Q2 body diode. The other two paths are the same with
the timeframe t2− t3.

18



2.4 DC-DC

Figure 2.15: Schematic operation at time interval t3− t4.

• Timeframe t4− t5

The operation schematic in this time interval is shown in Fig.2.16.

At t4− t5, QA and QD are off. QB is turned on together with the QC on state. The
transformer secondary side current is flowing through QC, the transformer winding as
well as QB as shown in Fig.2.15. The power transfers from the transformer secondary
side to the tertiary side and will generate a negative VT as shown in Figure2.11.

This time period is quite similar with the process in timeframe t0− t1. On the tertiary
side, SR1 is already on and SR2 is off. No current will flow through Q2 and all the
transfer current is passing through Q1. The current will be separated into the two paths
trough L2 and L3. The current flowing through the L2 will keep increasing due to the
negative force transformer voltage VT. However the L1 current will decrease with the
freewheeling stored energy in L1.

Figure 2.16: Schematic operation at time interval t4− t5.

19



Chapter 2. Theory

• Timeframe t5− t6

The operation schematic in this time interval is shown in Fig.2.17.

At t5, QC turns off and the other MOSFETs keep the same states. The stored energy of
Lr forces Ip to keep flowing with its value at t5, which will lead to a start of charging
the QC COSS and discharge QD COSS. If Ip is adequate as mentioned before, the voltage
of the drain of QD, or the source of QC, will resonate from Vi,max to zero to achieve
ZVS. After realizing ZVS, the current Ip stops flowing through the Coss instead the QD
body diode is turned on and Ip still keeps flowing through it.

At t5, the forced voltage VT will change to zero and the energy stops flowing now.
Since VDS of Q2 is reaching zero voltage in this period and the Q2 body diode is on. At
the secondary side the current keeps almost the same value, the current of the tertiary
side transformer is almost the same value as at t5. As a result, the body diode current
Q2 will increase slowly from zero. Together with the two existing current paths in the
time period t4− t5, the current through the Q2 diode and L2 behave as the third path.

Figure 2.17: Schematic operation at time interval t5− t6.

• Timeframe t6− t7

At t6, QD starts to turn on. The secondary current will shift the current to the QD MOS-
FET from the body diode. As shown in Fig.2.18, the current keeps flowing through
QB, the transformer, and QD with almost the same value.

On the tertiary side, SR2 turns the MOSFET Q2 on. Since the Q2 body diode is on
previously, the VDS of Q2 is zero. ZVS occurs in the turn-on switching of Q2. Now the
current is passing by MOSFET Q2 instead of the body diode. These other two current
approaches are the same as mentioned for the time period t5− t6.

20



2.4 DC-DC

Figure 2.18: Schematic operation at time interval t6− t7.

• Timeframe t7− t0

t7− t0 is the last period of the repeated charging sequence. QB is off at t7. The leakage
inductance stored energy forces the current to still flow with its value at t7, which will
start to discharge QA COSS and charge QB COSS as shown in Fig.2.19. If Ip is adequate,
the voltage of the drain of QB, or the source of QA, will resonate from zero to Vi,max.
After the voltage of the drain of QB, or the source of QA, reaches Vi,max, the current
Ip stops flowing through the COSS, instead turns on the body diode of QA and continues
to flow.

At t7, the voltage of the QA source or QB source is resonated from the maximum value
to zero voltage. In this short time, VDS of QB will reach zero voltage and the body
diode will turn on. Since the secondary side current keeps almost the same value, the
transformer tertiary side is the same of the value at t7. As a result, the body diode of
Q1 will take all the current of the Q1 MOSFET at t7. The charging path changed from
the MOSFET Q1 to the body diode of Q1. And the other two current paths are the
same as those in the time period of t6− t7.

21



Chapter 2. Theory

Figure 2.19: Schematic operation at time interval t7− t0.

2.5 Transformer

The transformer plays a significant role in the converter design. On one hand, it has the
function to transfer power, change voltage as well as make the isolation. On the other
hand, it affects a lot of the converter volume and efficiency. Especially in this thesis’
case, the three winding transformer will combine the OBC and DC-DC converter to-
gether to reduce volume. The inductive coupling between the primary and secondary
windings can transfer the energy from the grid to power the HV battery. In addition to
that, a third winding is added. By the inductive coupling between the secondary and
tertiary side, it brings the high battery voltage down to the 12V load at the output for
supplying auxiliary network loads. In this thesis work, the three winding transformer
will be designed accordingly for the rated voltage and current. Also it aims to achieve
higher efficiency with the new transformer structure.

The three winding transformer losses need to be considered carefully. The losses in
a transformer are core loss and copper losses. The core loss strongly depends on
the material that is chosen for the transformer core, which could be basically called
hysteresis loss and eddy currents loss. In order to calculate core loss, the Steinmetz
equation is introduced here.

Pv = k f a
sw(M Bmax)

b (2.8)

where Pv is time average power loss per unit volume, f is switching frequency in kHz
A and B is the peak flux density in T. K,a,b are material parameters. Hence, the total
core losses can be decided as

Pcore = PvVe (2.9)

where Ve is the core volume.

22



2.6 Semiconductor losses determination

Copper loss refers the losses generated when the current flows through the copper
wires. When the three winding transformer is working, only two sides are active, we
can calculate the copper losses of the OBC and separately.

First, one must determine the total resistance of the copper wires. Since the length
of one turn could be found in the core shape datasheet, the total length of the copper
wires can be defined with the help of turn numbers.

Lpri,winding = LturnN1;
Lsec,winding = LturnN2;
Lter,winding = LturnN3;

(2.10)

Secondly, the resistance of copper wires can be calculated.

R1 =
ρcuLpri,winding

A1,bundle
;

R2 =
ρcuLsec,winding

A2,bundle
;

R3 =
ρcuLter,winding

A3,bundle
;

(2.11)

where ρcu is the copper resistivity. ρcu is temperature related. Usually, ρcu is 1.7 ∗
10−8Ωm in normal temperature. When the transformer is working, however, the tem-
perature is much higher than 25◦C. Hence ◦C is set to 2.02 ∗ 10−8Ωm according to
N87 datasheet.

The copper losses for OBC and DcDc can be quantified by the following expression.

Pcu,highpower = R1I2
1,rms +R2I2

1,rms;

Pcu,lowpower = R2I2
22,rms +R3I2

3,rms
(2.12)

Eventually, the maximum power dissipated in the transformer is figured out as

Ptotal,OBC = Pcore,OBC +Pcu,OBC (2.13)

Ptotal,DcDc = Pcore,DcDc +Pcu,DcDc (2.14)

2.6 Semiconductor losses determination

When talking about the semiconductor losses, it usually refers to switching and con-
duction losses. When the semiconductor is turned on and off, the losses is called
switching losses. When it is conducting, conduction losses occur. The semiconductor
voltage and current waveforms during one conduction period are plotted in Fig.2.20

23



Chapter 2. Theory

Figure 2.20: Semiconductor losses.

2.6.1 Switching losses

When the control signal is set to ON, it starts with turn on losses. As Fig.2.20 indicates,
the voltage decrease from the max value to zero voltage and the current increase from
zero to max voltage. One triangle is formed and marked red to show the power over
the switch when turning on. tri is the rise time and t f v is the turn on delay time. Vd is
the voltage between gate d and s when the MOSFET turning on and I0 is the current.
Consequently the turn on losses is

Pon =VdI0
tri + t f v

2
fs (2.15)

As the turn off process, t f i is the fall time and trv is the turn off delay. Similarly the
turn off losses could be found as

Pon =VdI0
t f i + trv

2
fs (2.16)

2.6.2 Conduction losses

When the MOSFET is conducting, it will behave as a resister, which will lead to
conduction losses. The conduction losses could roughly be calculated as

Pon−state = RdonI2
on(rms) (2.17)

24



2.7 Topology overview

Among them, Rdon is the on-state resistance and the value could be easily got from the
MOSFET datesheet. Ion(rms) is the calculated RMS current during conduction.

In reality, however, there is one body diode in anti - parallel with the MOSFET in the
switch module. It will the carry reverse polarity current. Besides, the diode usually
starts conducting before the MOSFET turning on to prepare the zero voltage switching.
Due to the forward voltage drop on the diode when the MOSFET is on-state, the
conduction losses can be found,

Von−state =Vsd +RdonIon(rms) (2.18)

Pon−state =
1
Ts

∫ DTs

0
ion(Vsd +RdonIon)dt (2.19)

=
Vsd

Ts

∫ DTs

0
iondt +

Rdon

Ts

∫ DTs

0
i2ondt

=VsdIon(avg)+RdonI2
on(rms)

For MOSFET Vsd is the forward voltage drop and can be found on the datesheet.Ion(avg)
is the calculated average current during conduction.

2.7 Topology overview

Figure.2.21 indicates the topology of the design which consists of the DC/DC part of
OBC and DC/DC converter for low power charging system. In order to reduce the
volume, the DC/DC for 12V battery charging is intended to integrate to the OBC part
with a isolated three-winding transformer which is a replacement of two conventional
transformers.

25



Chapter 2. Theory

Figure 2.21: The topology of the combined OBC and DC-DC converter.

26



3
Case set up

3.1 Specification

As this thesis work has defined, the specifications for these two charging paths are
shown in Table 3.1 and 3.2.

Table 3.1: Specifications of the high power charging path

Input AC phase voltage from grid Vi 110V −240V

Maximum value of the input current from the grid 16A

AC line frequency 50Hz

Output power 3.6kW

Output dc voltage 250V −400V

Output voltage ripple Less than 2V(peak to peak)

Maximum output current 11A

Switching frequency of the DC-DC stage, 100kHz

Efficiency over 94%

Table 3.2: Specifications of the low power charging path

Input dc voltage range,Vi 330V −420V

Output power 2.5KW

Output dc voltage,Vo 10V −16V

Output voltage ripple peak to peak around 4%−5%

Output current 182A

Switching frequency, fs 100kHz

Efficiency over 90%

27



Chapter 3. Case set up

3.2 Passive components selection

3.2.1 DC-DC part of OBC resonance inductance selection

The leakage inductance add the external inductance L for ZVS achievement can be
derived by the minimum principle of ILrms_max. The target is to decrease the losses by
finding out a suitable inductance value which is corresponding to the optimized lower
RMS current. According to the principle of DAB, the energy is transferred by the in-
ductance between the power source and battery, the value of the inductance determines
the ability of the power transfer. Hence, the minimum value of the maximum power
transfer must be large than the rated power.

kmin
V 2

1
8L fs

= 0.66× 4002

8×L×105 ≥ 3600 (3.1)

⇒ L 6 36.67µH (3.2)

There is a relation between the inductance L and the maximum rms value of the in-
ductance current ILrms_max. This can be observed from Fig3.1, where there is an opti-
mized L making ILrms_max to be the minimum value, which means L = 21.966µH and
ILrms_max = 16.147A. The inductance value is used for realizing the ZVS operation
with the parasitic output capacitance of the semiconductor.

Figure 3.1: The waveform of ILrms_max corresponding with L.

28



3.2 Passive components selection

3.2.2 DC-DC Passive components selection

The filter inductance play an important role in the current doubler design. It mainly affects
the output current ripple. The output current I0 is the sum up of the current flowing these two
inductance IL1 and IL1(I0 = IL1 + IL2). Hence the filter current will cancel some ripple. Here
a cancel coefficient K is set to present the relationship between ∆i0 and ∆iL. ∆i0 is the output
current ripple and ∆iL is the inductance current ripple.

∆i0 = K∆iL (3.3)

where,

∆i0 =
(1−D)TV0

L0
(3.4)

∆iL =
(1− D

2 )TV0

L0
(3.5)

As a result, one can calculate,

K =
∆i0
∆iL

=
1−D
1− D

2
(3.6)

∆i0 = (1−D)
V0

2L f fs
(3.7)

Consequently, when D = 1, the out put current ripple will be zero. To decrease the filter
inductance, the best situation is to let D to be near 1.

In this design, the duty cycle of DC/DC converter at the rated voltage is

D =
2V0N
Vin

= 0.64 (3.8)

The cancel coefficient K is

K =
1−D

1−D/2
=

1−0.64
1− 0.64

2

= 0.53 (3.9)

According to the max current ripple and K, the output inductor ripple can be calculated as

∆iL =
∆i0
K

= 33.7A (3.10)

Accordingly, the output filter inductor is

L f = L1 = L2 =
V0(1− D

2 )

∆iL fs
= 2.8µH (3.11)

The output filter capacitance C f mainly affects the output voltage ripple. If the filter capac-
itance is quite small, there be large voltage ripple. By comparison, the large output capaci-
tance will lead to a big package volume. It is of great importance to choose the appropriate
capacitance. The following relation must be fulfilled as

C f =
V0

8L f (2 fs)2∆Vopp
(1− V0

Vin/n
) (3.12)

The output capacitance is selected to 200µF

29



Chapter 3. Case set up

3.3 Operation frequency

High frequency power conversion systems are attracting more and more attentions in industry
for high power density, reduced weight, and low noise without compromising efficiency,
cost, and reliability[10]. To study the suitable operation frequency, the losses and the volume
of the transformer have been investigated under different frequency. Since the losses in the
transformer increases obviously with a nearly saturated flux density under 100kHz, and the
switching loss of the converter rises rapidly above 100kHz. In this case, 100kHz is chosen
as the switching frequency.

3.4 Component selection

3.4.1 Semiconductor selection

The transistor as switch plays a crucial role in the charging system with respect to switching
speed and power loss. Nowadays, IGBTs and MOSFETs are widely used in electrical sys-
tems for PHEVs. For the low switching frequency(less than 50kHz) and high rated voltage,
the IGBT is probably the best choice. But for the higher switching frequency, the MOS-
FET is better than the IGBT. According to the design specification, the operating frequency
is 100kHz and voltage range is about 10V to 400V. So, the best transistor is probably the
MOSFET in this supply range.

For the high power charging path, the withstanding voltage across the transistor on the pri-
mary side of DAB is equal to the input voltage V1 = 400V , the voltage of the secondary side
for the transistor is the upper limit of the battery voltage 400V . The peak current is of the
transistor on the primary side is about 24A based on calculation from the (2.6). For choosing
the appropriate rating for the semiconductors, the voltage and current safety margin should
be kept for the transistors. So the IPW65R048CFDA from Infineon is chosen for being the
semiconductors on the primary side.

The IPW65R048CFDA from Infineon is an automotive qualified technology with a inte-
grated fast body diode on the market. Its rated voltage reaches 650V which meets the suit-
able safety margin. And from the data sheet, the maximum conduction current is 63.3A at
25 ◦C and 40A at 100 ◦C.

The same procedure is carried out on the secondary side. Since the withstanding voltage of
the MOSFET is also 400V and the turns ratio is 0.8, which means that the current is almost
the same as the primary current. So the IPW65R048CFDA from Infineon is selected for both
the primary and secondary sides in high power charging path.

Still the same procedure is conducted for the MOSFETs used for the tertiary winding side,
but the ratings are different. The peak voltage they need to stand is 40V . For the peak
current, the number is approximately 200A. According to the procedure mentioned before,
IRFP2907 is selected. IRFP2907 is an automotive MOSFET from International Rectifier. It
is designed for 42 volts automotive electrical systems. Its rated voltage can reach to 75V and
the maximum conduction current is 209A.

30



3.5 Transformer design

3.5 Transformer design

The three winding transformer design plays an important role in this master thesis. This part
will go through the transformer design procedure and how to choose the best transformer
according to the transformer losses and its working flux density.

3.5.1 Turns ratio determination

To determine the turns ratio of the three windings transformer, the turns ratios between
N1/N2 and N2/N3 needs to be figured out separately, then the general relationship could be
found.

When the input voltage stays at a lower level, the transformer could still make the output
voltage stay at the rated value. To start with the high power charging path, the voltage of the
secondary side is as VT . The maximum duty cycle on the secondary side is Dsmax. Hence,
the minimum voltage should be

Vsmin =
VT

Dsmax
(3.13)

The turn ratio is determined as
N1

N2
=

Vin

Vsmin
(3.14)

Similarly, the turns ratio of N2
N3

can be settled using the same procedure.

3.5.2 Core Design

Nowadays, a lot of magnetic materials and structures are widely used in industry. They differ
by losses per unit, prices, recommended operational frequency, magnetic properties, density
etc. There are three main groups of magnetic core used today. They are ferrite cores, metal
alloy tape-wound cores and powdered metal cores. Among them, ferrite cores, are selected
due to their standard working high frequency ability. Ferrites have been known for a long
time. They are ceramic materials which mostly consist of iron oxide with such additives as
oxides or carbonates of manganese and zinc or nickel and zinc. A ferrite core has the feature
of a low coercivity. Hence they are named as "soft ferrites" which means the material’s
magnetization can easily reverse direction instead of dissipating much energy (hysteresis
losses). Due to the different iron oxide contents, the ferrite core has different types such as
N82, N87, N92 and so on.

When the core material is decided, a core shape must be decided. One important condition
is that the window area of the transformer must be large enough to fit the three windings
together inside. Here the E series is choose due to its large window area, Besides, the winding
is also expected to have a larger contact with the air, which will be a benefit for cooling. To be
specific, EE, EC, ETD are all belong to E series cores. Among them, ETD core is selected
since its dimension is optimized for a better transformer efficiency. The one turn length
of ETD is smaller than that of EE and EC core. So the winding resistance is minimized.
Consequently, copper losses will be less and it will lead to a lower temperature raise.

31



Chapter 3. Case set up

Basing on the products provided by the supplier of TDK, the ETD core has two different
ferrite materials. One is N87 and the other is N97. N87 is the standard transformer material
when the transformer is working under 500kHz. Due to its lower price and lower losses, N87
is a better choice. It is ferrite core with base material of MnZn. The peak flux density it can
withstand is 0.39T.

A conventional design procedure is defining the number of turns, calculating flux levels and
checking whether they fit in the core. When determining the turns number according to the
turns ratio, one must make sure the core would not be saturated since the number of primary
turns also affects the peak flux density B̂core in the core. As a result, it can start the primary
turn number determination based on the working flux with help of Faraday’s Law,

e(t) = N
dφ

dt
Am (3.15)

⇒V (t) = N
dB
dt

Aw (3.16)

B = B̂cos(wt)⇒V1(t) = N1Aw
dB̂
dt

cos(ωt) (3.17)

⇒V1 = N1AwωBsin(ωt) (3.18)

⇒V1 = N1AwωBcore (3.19)

Since the magnetic flux can be decided by

φ = AwB̂core (3.20)

To explain, V1 is the primary side voltage which is varying with time. Aw is the core effective
area and dφ

dt is the time derivative of the magnetic flux in the core.

Combining 3.20 and 3.17, the following relation is found∫ DTs

0
V1dt = N1Aw

∫ Bcore

−Bcore

dB (3.21)

When there is an active power transfer through the transformer, it will generate the voltage
V1 applied over the primary side. Besides, this voltage will create the flux density in the
transformer, which will be changing from negative to positive peak flux density every period.

In 3.21, it can be seen that the flux density highly depends on the input voltage applied on
the transformer. In other words, if the duty cycle DTS is changing, the peak flux density in
the core B̂core or N1 will also be changing accordingly. To define the appropriate transformer
core, the maximum input voltage and the maximum duty is considered. Hence the turn can
be found by the expression

N1 =
Vd,maxDmaxTs

2AmB̂core
(3.22)

If the number of turn is determined, the equation can be also used to calculate the peak flux
density.

32



3.5 Transformer design

B̂core =
Vd,maxDmaxTs

2AmN1
(3.23)

3.5.3 Winding Design

To calculate the cross - sectional area of the wiring, the RMS current values when the three
winding transformer working at the nominal load needs to be calculated first. Due to the
operational high frequency in the charging system, Litz wire is suggested as to increase the
conductor area while maintaining a low skin effect as well as low proximity losses. Tens,
hundreds, or more strands of small-gauge insulated copper wire are bundled together, and
are externally connected in parallel. These strands are twisted, or transposed, such that each
strand passes equally through each position inside and on the surface of the bundle. This
prevents the circulation of high-frequency currents between strands. To be effective, the
diameter of the strands should be sufficiently less than one skin depth. Also, it should be
pointed out that the Litz wire bundle itself is composed of multiple layers.[9]

Considering the thermal issue in this design, the current density is chosen as 4.5 A/mm2.
Next, the cross-section of each winding can be calculated based on the RMS current and the
current density,

Abundle =
IRMS

J
(3.24)

where Abundle is the total area of each winding and J is the current density with the value of
4.5 A/mm2.

In general, the maximum single wire diameter should be smaller or equal to nearly a third of
skin depth,

d =
1
3

δ (3.25)

d is the diameter of one single wire and the skin depth δ = 7.5√
f = 0.2377mm at T = 100◦.

Now the number of strands in each winding can be determined by

Astrand =
Abundle

πr2 (3.26)

where r is the radius of the single wire.

Finally, using the data information from the Litz wire supplier called Elektrisola to check
which series of Litz wire matches the design according to the calculation above. In this
design, the copper fill factor is assumed to be Kcu = 0.45. Then the winding area equation
related with Kcu is achieved.

Awinding =
A1,bundleN1 +A2,bundleN2 +A3,bundleN3

Kcu
(3.27)

where the Awinding is the window area of the core and N1,N2,N3 are the transformer turns.

33





4
Results and analysis

4.1 Topology simulation results

The total topology with selected MOSFETs is shown in Fig.4.1.

Figure 4.1: Dual active bridge converter and current doubler synchronous rectification.

In this section, the high power charging path with a dual active bridge structure and the low
power charging path with current doubler topology will investigated separately. Both of the
models are set up and simulated in LTspice. The parameters of the components are taken
from the data sheets that were mentioned before. And the MOSFET’s model are also taken
from the Infenon supplier. In this model, MOSFETs are defined by the on-state resistance
RDS(on), the forward voltage drop Vf , the parasitic output capacitance and the embedded body
diode.

35



Chapter 4. Results and analysis

4.1.1 OBC charging path simulation and analysis

For the high power charging path, the simulation results of the Dual active bridge converter
are presented. On the primary side, one voltage source with 400V acts the output of the in-
terleaved boost converter and on the secondary side, a voltage source with a series resistance
is used to imitate the battery model in simulation. To decrease the oscillation, the turn-off
pure capacitive snubber circuit is added in the design.

The simulation setup is according to the one introduced to Chapter 3.3.1. The duty cycle of
each switch is selected to be less than 50% so as to achieve zero voltage operation during
the switching transient. The drive signal for the switches are marked in blue colour and the
voltage waveform over each switch is shown as red colour in simulation. According to the
simulation and the obtained waveforms, ZVS is successfully achieved both on the primary
side and the secondary side, which are shown from Figure 4.2 to Figure 4.7. It can be clearly
seen that the switch voltage for each switch goes up after the gate signal reaches zero during
turn-on transition and the switch voltage decreases to zero before the gate signal increases
during a turn-off interval. To realize the soft switching operation, the transistor is modeled
with an anti parallel diode, a parasitic capacitance, and the sum of leakage inductance with
an external inductance.

For instance on the primary side, when the switch Q1 turns off, the inductor current will
charge the parasitic capacitance C1 and discharge the parasitic capacitance C2 of Q2 until
the voltage of C2 reaches zero. Then the current will flow through the body diode D2. After
that, the switch Q2 can be turned on at zero voltage and the inductor current will freewheel
both though the switch and the diode until the current changes into the positive direction.

The other switches operate followed the same principle that explained in detail on chapter
3.3.1. To achieve ZVS operation, the stored energy in the inductor must be large enough to
fully charge and discharge the parasitic capacitance from zero to the switch voltage and vice
verse.

Figure 4.2: ZVS switching for transistor Q1 of DAB.

36



4.1 Topology simulation results

Figure 4.3: ZVS switching for transistor Q2 of DAB.

Figure 4.4: ZVS switching for transistor Q3 of DAB.

Figure 4.5: ZVS switching for transistor Q4 of DAB.

37



Chapter 4. Results and analysis

Figure 4.6: ZVS switching for transistors Q5 and Q8 of DAB.

Figure 4.7: ZVS switching for transistors Q6 and Q7 of DAB.

Figure 4.8 and Figure 4.9 show the simulation results of the transformer voltages on primary
and secondary side. Based on the phase-shift control, the inner phase-shift ratio on the
primary side is adding to expand the ZVS range. In this switching pattern, the voltage on the
primary side is becoming a three-level waveform while the voltage on the secondary side is
a two-level square waveform. During the time intervals of the zero voltage of the three-level
waveform, the back-flow power is zero which means the circuiting power decreases.

38



4.1 Topology simulation results

Figure 4.8: The voltage on the primary side of the transformer in DAB.

Figure 4.9: The voltage on the secondary side of the transformer in DAB.

The output voltage and output current are shown in Figure 4.10, and from the simulation
result it can be seen that, the voltage ripple is less than 2V due to the output filter.

Figure 4.10: The output voltage and current of the OBC.

39



Chapter 4. Results and analysis

4.1.2 DC-DC topology simulation and analysis

For the DC-DC phase - shift full bridge converter and current doubler synchronous rectifier
topology, the simulation parameters is set according to the Chapter.3.2.2. In this chapter, the
simulation results and waveform will be covered and analyzed.

First, the drive signal for the four switches on the secondary side is set according to Fig.2.11.
The waveform is shown in Fig.4.11. The blue and magenta are the drive signal for QA and
QB. And red and green are to drive MOSFET QC and QD.

Figure 4.11: Drive signal for MOSFETs .

It can be seen that a switching frequency of 100kHz is applied (T = 10µs). The duty cycle
is chosen to be slightly lower than 50%. Therefore, the blanking time between the switches
has the ability to prevent short-circuit of one leg. There is also a phase shift between leg A/B
and leg C/D. This will help to control the transformer primary side voltage.

The voltage and current behavior analysis is shown in Fig.4.12. In subfig 3, the green line
refers to the transformer secondary side voltage and the purple refers to the current. It is
seen that when MOSFET QA and QD are both conducting, the transformer will transfer
the positive voltage from the secondary side to the tertiary side displayed as the positive
green voltage around 330V . Similarly, when QB and QC are conducting, it will transfer the
negative voltage to the tertiary side as the −330V transformer primary output voltage. With

40



4.1 Topology simulation results

the energy flowing, the current will increase doing the non-zero voltage period. When QA
and QC, or QB and QD are conducting, as the phase shift happens, there will be no power
flowing through the transformer. It is indicated as the zero voltage in the 4.12. The current
is decreasing in the same time period.

Figure 4.12: Voltage and current behavior analysis in the secondary transformer side .

Regarding the ZVS achievement on the DC-DC full bridge converter, it is found to work
very well using simulation. The operation can be seen from Fig.4.13 - 4.14. The blue curve
is the gate-source voltage and red is drain source voltage. For each MOSFET, it is clearly
shown that when Uds has already reached zero, Ugs would begin to rise. There is no overlap
and ZVS is achieved, which reduces the full bridge switching losses.

41



Chapter 4. Results and analysis

Figure 4.13: MOSFET QA zero voltage switching.

Figure 4.14: MOSFET QA zero voltage switching.

42



4.1 Topology simulation results

Figure 4.15: MOSFET QA zero voltage switching.

Figure 4.16: MOSFET QA zero voltage switching.

The synchronous rectification current doubler topology is implemented on the third side of
the three winding transformer. The signal operation to SR1 and SR2 are shown in Fig.4.17.
The green curve stands for the drive signal of MOSFET SR1 and the red curve is for the
drive signal of MOSFET SR2. The synchronous rectifier behaves by following the power
transferred from the transformer primary side. It can be seen that when transformer voltage
is positive, MOSFET SR1 is turned off. By contrast, if VT is negative, MOSFET SR2 is
turned off.

43



Chapter 4. Results and analysis

Figure 4.17: Drive signal for MOSFETs on the tertiary side .

Fig.4.18 is the current analysis on the tertiary winding. The red and blue curve stand for the
current flowing the inductors and the green one is the output current. Each filter inductor
will pass half of the output current with ripples. These ripple will be reduced after they add
together and flow as the output current with much more smooth current around 180A. The
lower limit value of output current is 169A and the high peak value is 187A, which meets the
design of 10% current ripple.

Figure 4.18: Current flowing through inductors.

Fig.4.19 shows the output voltage curve. It is indicated that the output voltage will increase
when the DC-DC starts converting. When the DC-DC operates in a stable state, the output
voltage is about 13.7V with a low ripple.

44



4.1 Topology simulation results

Figure 4.19: Output voltage.

45



Chapter 4. Results and analysis

4.2 Transformer selection

Transformer design and selection are keys to this thesis. In this chapter, the focus will be
on the core and winding design. The two-winding transformer for the OBC and DC-DC
will be discussed first, and then finally a three winding transformer will be introduced and
compared.

4.2.1 Turns determination

In this section, the core of the winging transformer and the is selected based on the working
flux, the transformer losses and whether the winding can fit the window area. According to
the turns ratio decided before, N1

N2 = 0.8 and N2
N3 = 7.7, seven turns groups are chosen and

will be further discussed here in Table 4.1.

Table 4.1: Available three winding transformer turns

N1 6 12 18 25 31 37 43

N2 8 15 23 31 39 46 54

N3 1 2 3 4 5 6 7

4.2.2 Core design

4.2.2.1 OBC isolated transformer

Based on the introduce in Chapter 3.6.2, the peak flux density is first calculated according to
3.30. The peak flux density in different cores as a function of the primary turn number for
OBC is shown as below.

Figure 4.20: Peak flux density in different cores as a function of primary number of turns at
100kHz for OBC path.

For the ETD cores series, there are seven types in total with different dimensions. Aw stands
for effective core area for each ETD core type. From the calculation result, it is seen that each
cell represents the peak magnetic flux magnitude formed in the cores with respect to the seven
turn groups. Since the maximum flux density of a N87 ferrite is 0.39T , the tables compare

46



4.2 Transformer selection

the formed peak flux density with this flux density limit and the cell colour represents the
suitability. The cell with red indicates exceeding the saturated value and the green shows
lower than it. Therefore, the green marked cells have the potential for being a choice.

Continuinga with the winding design, Fig. 4.21 shows whether the winding could fit in
the core window area. The values are positive meaning that the winding size is smaller
than the bobbin and could fit in. By contrast, negative values indicate that the winding will
not be applicable for the transform bobbin. Combined with the values from the Fig.4.20,
consequently, the green marked cells are potentially suitable to work on.

Figure 4.21: Differences between the core window area and the windings area.

To get a better transformer efficiency, the transformer core loss and copper loss are calculated
and presented in Fig. 4.22 and Fig. 4.23 to help with the selection, where Ve presents the
effective magnetic volume in cm3 and Ln stands for the average length for one turn in mm.

Figure 4.22: OBC transformer core losses.

Figure 4.23: OBC transformer copper losses.

Usually the least total losses design is preferred. When the losses will not make too much
difference, prefer to have the core with smaller dimension and windings with less turns to

47



Chapter 4. Results and analysis

save the cost and reduce volume. Compared the losses difference, it is seen that core type
ETD 54/28/19 with the winding of N1 = 25 and N2 = 31 has the roughly equal core and
copper losses. The size of ETD 54/28/19 is 54 x 56 x 22 mm and it consists of two pieces.
The final total losses are the transformer is 12.45W shows in Fig. 4.24 with a efficiency of
99.65%.

Figure 4.24: OBC transformer total losses.

4.2.2.2 DC-DC isolated transformer

Similar as the OBC transformer introduced in Chapter 4.2.2.1, the peak flux density in dif-
ferent cores as a function of the turn number for the DC-DC is shown as below. To easily
look up the ratio relationship in Table 4.1, the primary turn number is still used for reference
and indication. The possible choices after flux density calculation are marked as green cells.

Figure 4.25: Peak flux density in different cores as a function of primary number of turns at
100kHz for DC-DC path.

After checking the area fitting of the transformer window and windings, the possible se-
lection are marked with the colour green and the discarded options are filtered with red in
Fig.4.26.

48



4.2 Transformer selection

Figure 4.26: Differences between the core window area and the windings area.

The calculated DC-DC transformer losses are shown in Fig.4.27 and Fig.4.28 respectively.
Based on the same design concept introduced, the ETD 59/31/22 core is selected due to the
least losses difference as well as a reasonable total losses. ETD 59/31/22 core size is 59 x
62 x 22 mm and contains two pieces. The two winding ratios are 31: 4. With a transformer
core loss of 3.8121W and copper loss of 9.7739W , the DC-DC transformer will have a total
loss of 13.586W and achieve an efficiency of 99.62% at rate power working point.

Figure 4.27: DC-DC transformer core losses.

Figure 4.28: DC-DC transformer copper losses.

49



Chapter 4. Results and analysis

Figure 4.29: DC-DC transformer total losses.

4.2.2.3 Three winding transformer

The same procedure will be conducted here. Since the three winding will not be working at
the same time, the the flux density will still be calculated separately as OBC and DC-DC in
the same working scenario. Therefore the result shows in Fig. 4.20 and 4.25 can be used for
this investigation.

Regarding the window area calculation, now the third winding is introduced and the possible
choices are shown in Figure. 4.30. Now the choices are reduced, and fewer cells could fit its
winding in the core window area.

Figure 4.30: Differences between the core window area and total three windings area.

With the flux density limit shows in Fig. 4.20 and 4.25, a new figure is obtained, presented
in Fig. 4.30. The choices are restricted in only these 8 groups.

Figure 4.31: Differences between the core window area and total three windings area.

50



4.2 Transformer selection

Since when the OBC and the DC-DC are working, the RMS current will be the same as in
the previous scenario, the copper losses will be the same as in the previous discussion. To
have least total losses, the core ETD 60/31/22 is selected with three winding turns set as
25/31/4. It has the largest dimension in this ETD core series and the transformer will be 60
x 62 x 22 mm and consists of two ETD core pieces.

When the primary and secondary winding of the three winding transformer are in operation
in the on board charger, the total losses is 11.295W marked in Fig.4.32 and the efficiency
is 99.67%. When the secondary and tertiary winding are transferring as DC-DC, the total
losses is approximately 13.586W marked in Fig.4.33 with and efficiency of 99.45%.

Figure 4.32: Total losses for OBC.

Figure 4.33: Total losses for DC-DC.

51



Chapter 4. Results and analysis

4.2.3 Winding

4.2.3.1 OBC transformer

To design and choose the Litz wire as introduced in Chapter 3.4.2, the two winding trans-
former used in on board charger is now conducted. A brief calculated winding bundle area
and strands number in each bundle for OBC transformer is shown in Table.4.4

Table 4.2: OBC transformer winding calculation

IRMS Abundle NStrand Litz type Litz length

Primary turn 16.14A 3.59mm2 714 4 bundle 180 strands 2.40m

Secondary turn 16A 3.56mm2 708 4 bundle 180 strands 2.96m

With the result presented, the Litz wire could be selected from the supplier Elektrisola.
Finally the OBC transformer winding is constructed by four bundles. Each bundle will have
180 strands inside and the cross section area of each bundle is 0.9048mm2. Based on the
core type ETD 54/28/19 and the winding of 25: 31 turns, the total length of four bundle Litz
wire will be 5.36m.

4.2.3.2 DC-DC transformer

Following the same approach, the strands number in each bundle for DcDc transformer is
calculated as NStrand,pri = 304, NStrand,sec = 2785. The primary winding is designed to be
five bundles and each bundle has 60 strands. The bundle cross section area is 0.3016mm2.
The five bundles of Litz wire with 600 strands in each bundle and of the cross section area
3.0159mm2 is utilized for the secondary winding. To fit the transformer core of the ETD
59/31/22 and winding turns of 31:4, 3.29m five bundle 60 strands Litz wire and 0.42m five
bundle 600 strands Litz wire are needed.

Table 4.3: DcDc transformer winding calculation

IRMS Abundle NStrand Litz type Litz length

Primary turn 8.30A 1.85mm2 307 5 bundle 60 strands 3.29m

Secondary turn 64A 14.20mm2 2785 5 bundle 600 strands 0.42m

4.2.3.3 Three winding transformer

As the three winding transformer, the calculation for each winding shall take the RMS cur-
rent scenario into consideration as the table below. For the primary and secondary winding,
the Litz wire used for OBC transformer will still be applicable here. The total length for four
bundle 180 strands will be 4.93m long. In addition, a 0.42m long 5 bundle 600 strands Litz
will conduct for the tertiary winding.

52



4.2 Transformer selection

Table 4.4: Three transformer winding calculation

IRMS Abundle NStrand Litz type Litz length

Primary turn 17A 3.77mm2 750 4 bundle 180 strands 2.65m

Secondary turn 16A 3.56mm2 708 4 bundle 180 strands 2.28m

Tertiary turn 64A 14.20mm2 2785 5 bundle 600 strands 0.42m

To compare the combined design with the signal OBC and DC-DC package, it is easily
verified that the the winded Litz length reduce a lot. A 0.43m-long 4 bundle 180 strands is
reduced and and no 5 bundle 60 strands Litz wire is needed.

53



Chapter 4. Results and analysis

4.3 Semiconductor losses

4.3.1 Semiconductor losses for OBC

The transistor losses normally consist of switching loss and conduction loss, which are cal-
culated using the equations mentioned in previous chapter.

Fig.4.34 shows the switching transition for Q2. The navy wave is the voltage over the tran-
sistor, the red wave represents the total current flowing through the MOSFET module and
the bluish one is the gate signal. For instance, before switch Q2 turns on, the capacitor dis-
charges the energy through the inductor, so the current goes down with the decreased voltage,
which can be observed from Fig.4.34. After the voltage decreases to zero, the current flows
in the anti-parallel body diode, thus, switch Q2 can be turned on with zero voltage. When
the gate signal is triggered, the MOSFET turns on, but the current flows both through the
MOSFET and the body diode according to the direction of the current. In Fig.4.34, only if
the current becomes positive, the MOSFET itself will conduct all current. Consequently, to
simplify the analysis and calculation, the switching conduction loss and the body diode will
be calculated together as conduction loss.

For simply analysis, the flowing current whatever its direction, is regarded as the current
going through MOSFET after the gate signal is triggered. Moreover, from the simulation
result it can be seen, ZVS operation is fully achieved for all switches in the OBC. Thus, the
semiconductor losses only consist of the transient loss caused by the body diode during the
blanking time and the conduction loss by switch itself.

Figure 4.34: The key waveforms for switch Q2 in DAB.

Figure.4.35 displays the current waveforms for each switch in one cycle. It is obviously seen
the half cycle starts from t0 and ends at t4.

According to the theoretical waves and the simulation results, the current on the typical point,
such as It0 , It1 , It2 , It3 and It4 can be calculated by (4.1) to (4.2) . Then different piecewise

54



4.3 Semiconductor losses

functions reflect the current waves which can be constructed in Matlab to calculate the typical
current values. Finally, the value of average current and rms current can be derived by
Matlab.

Figure 4.35: The current waveforms for each switch.

• Time interval between t0 to t2:

i(t) =
(1+ k)V1

L
(t− t0)−

(Dy1 + kDy1 +2kDφ −2k)V1

4L fs
(4.1)

• Time interval between t2 to t3:

55



Chapter 4. Results and analysis

i(t) =
(1− k)V1

L
(t− t2)+

(k+2Dφ −1)V1

4L fs
(4.2)

• Time interval between t3 to t4:

i(t) =
−kV1

L
(t− t3)+

(Dy1− kDy1 +2kDφ )V1

4L fs
(4.3)

Based on the analysis of Chapter 2.3.2, regarding switch Q1, during blanking time before
turning on, the current flows through the body diode during one period. Then the current
will run through Q1 itself when it is on. Here is the analysis procedure in detail for one
period from t0 to t8 .

• Time interval between t0 to t2:

Q1 is on status and the switch current is negative from t0 and reaches zero at t0 then flows in
positive direction, thus It0 = -7.48A according to (4.1).

• Time interval between t2 to t3:

The current flows positive through Q1 in this period. According to (4.1) and (4.2), the instant
current at t2 and t3 can be calculated as It2 = 4.92A and It3 = 24.54A.

• Time interval between t3 to t7:

Q1 snaps off during this period, therefore, the current is zero.

• Time interval between t7 to t8:

From t7, Q1 starts up for another half cycle operation. During the blanking time between
t7 and t8, the current flows through the body diode of Q1 reversely. From the figure can be
seen, It7 =−It3 . Hence, It7 =−24.54A and It8 =−20.8A.

• Time interval between t8 to t0:

The current is still negative through Q1 and the current wave from t7 to t0 is symmetric with
the current in the figure from t3 to t4.

Then these current values are imported to Matlab and the average current and rms current
can be finalized. Consequently, the semiconductor losses for Q1 is calculated as

Pon−state−Q1 =VsdIon(avg)+RdonI2
on(rms) =

0.9V ·22.67A+0.043Ω · (3.82A+15.782A+14.142A)≈ 40W

Rdon is the on-state Resistance of MOSFET and is chosen with the value of 0.043Ω under
25◦ based on the MOSFET IPW65R048CFDA specification in this case.

As the current wave of Q2 is symmetrical and there is only a half cycle phase shift compared
to Q1, therefore, the semiconductor losses is the same as Q1. Other switches follow the same

56



4.3 Semiconductor losses

analyzing procedure with the similar operational mechanism. The waves of Q3 and Q4 are
symmetric with 180◦ phase shift. Therefore, the semiconductor losses for Q3 and Q4 are

Pon−state−Q3Q4 =VsdIon(avg)+RdonI2
on(rms)

= 0.9V ·3.74A+0.043Ω · (2.822A+13.772A+16.752A)≈ 24W

On the secondary side, the two switches in each arm are conducting 180◦ complementary and
the diagonal switches operates simultaneously. So the waveforms of Q5 and Q8 are identical
and the waveforms of Q6 and Q7 are only 180◦ phase shifted compared to Q5 and Q8. The
current value on the secondary side is proportional to the primary side current with the value
of transformer turns ratio. Therefore, according to the theoretical current waveforms and
simulation, the power losses of each switch can be defined.

Pon−state−sec =VsdIon(avg)+RdonI2
on(rms)

= 0.9V ·2A+0.043Ω · (12.622A+13.42A)≈ 16.5W

Consequently, the semiconductor power losses for OBC can be calculated as

Pon−state−tot = 2Pon−state−Q1 +2Pon−state−Q3Q4 +4Pon−state−sec

= 2 ·40W +2 ·24W +4 ·16.5W = 194W

57



Chapter 4. Results and analysis

4.3.2 Semiconductor losses for DC-DC

4.3.2.1 DcDc full bridge topology semiconductor losses

As the simulation result shows in Chap. 4.1.2, zero voltage switching is well achieved for
the four MOSFETs on DC-DC full bridge. It is clear that the conduction losses will be the
main dominant part. Based on (2.18) introduced, the conduction loss for one MOSFET can
be found to be

Pon−state =VsdIon(avg)+RdonI2
on(rms) = 7.8W

Regardless of the switching losses due to good result of ZVS, the total semiconductor losses
of the DC-DC full bridge in one period is

Ptot,sec = 4∗Pon−state = 31.4W

4.3.2.2 DC-DC current doubler topology semiconductor losses

To calculate the semiconductor losses in the DC-DC output topology synchronous rectifier
losses, the conduction process in one cycle could be divide into the following four periods
in specific as shown in Fig 4.36. Combined with the simulation result shown in Fig.4.18 and
Fig.4.19, the losses will be calculated in the following part.

Figure 4.36: Losses analysis of synchronous rectifier.

58



4.3 Semiconductor losses

• Timeframe t0− t1
Id(avg) = ILav + ILav = 2ILav = Io (4.4)

VDS = RdonId(avg) = RdonIo (4.5)

Pd1 =
DTs

Ts
Id(avg)VDS = DRdonI2

o = 0.36 ·3.6 ·10−3 ·1802 = 41.9W (4.6)

• Timeframe t1− t4

The losses in this period is calculated as

Id(avg) = Io +Ts(
Vo

4L
− DVo

2L
) (4.7)

VDS = RdonId(avg) = Rdon[Io +Ts(
Vo

4L
− DVo

2L
)] (4.8)

As a result the loss is

Pd2 =
(0.5−D)Ts

Ts
Id(avg)VDS (4.9)

= (0.5−D)Rdon[Io +Ts(
Vo

4L
− DVo

2L
)]2

= (0.5−0.36) ·3.6 ·10−3 · [180+10−5(
13.5

4 ·2.8 ·10−6 −
0.36 ·13.5

2 ·2.8 ·10−6 )]
2 = 16.9W

• Timeframe t4− t5

In this time period, the losses the the MOSFET turn off losses. According to2.6.1, it is
calculated

Pd3 = Pon =VdI0
t f i + trv

2
fs

= 13.5 ·180/2 · (130+130) ·10−6

2
·105 = 1.6W

• Timeframe t5− t0

Id(avg) = Ts(
Vo

4L
− DVo

2L
) (4.10)

VDS = RdonId(avg) = RdonTs(
Vo

4L
− DVo

2L
) (4.11)

As the result, the loss is calculate

Pd4 =
(0.5−D)Ts

Ts
IdVDS = (0.5−D)Rdon[Ts(

Vo

4L
− DVo

2L
)]2 (4.12)

59



Chapter 4. Results and analysis

= (0.5−0.36) ·3.6 ·10−3 · [10−5(
13.5

4 ·2.8 ·10−6 −
0.36 ·13.5

2 ·2.8 ·10−6 )]
2 = 0.05W

Based on the above calculation for one MOSFET in one conduction period, the total DC-DC
current doubler loss during one conduction could be get as

Ptot,ter = 2∗ (Pd1 +Pd2 +Pd3 +Pd4) = 120.45W (4.13)

60



4.4 Efficiency

4.4 Efficiency

4.4.1 Efficiency of OBC path

The efficiency of the DAB is evaluated using real transistor model from Infineon and calcu-
lated in nominal operation point which means the output voltage is the nominal voltage of
the battery with the value of 330V .

In full load condition, the output power is around 3.750kW in steady state. The semiconduc-
tor losses with 194W and the transformer losses with 12.45W are calculated from previous
section. Hence, the efficiency at nominal point of the high power charging path is 94.8%.

4.4.2 Efficiency of DC-DC path

The DC-DC loss can be obtained from the previous calculation. It is conducted based on the
theoretical analysis and the LTspice simulation waveform. In the full load condition with an
input power of 2.5kW , the total losses will be 160.67W and achieve an efficiency of 93.57%.
The output power will be 2.34kW

Ptotal = Ptot,sec +Ptrans +Ptot,ter = 31.4+8.82+120.45 = 160.67W

61



Chapter 4. Results and analysis

4.5 Design comparison

A simple transformer comparison is made in Fig.4.37 based on efficiency, component price
as well as the rough transformer volume. It is shown that the efficiency reduces a little with
the three winding transformer conducting for the OBC. The volume is reduced a lot since
one one ETD 59/31/22 core will be used. In terms of the component price, based on the
local RS component online shop and E-bay, three winding transformer is much more cost
effective by reducing about 35%.

Figure 4.37: Transformer comparison.

Based on the comparison above, a further general cost of the power electronic devices are
listed. On one hand, the new design reduces the package dimension. On the other hand, the
total cost of the key component is much lower. It eliminates one transformer core. More
importantly, only ten MOSFETs are used instead of total fourteen MOSFET working on
two PCBs, which makes the combined OBC and DC-DC much more promising and cost
effective. In an rough summary, it could saves about 613 Sek for the new combined package
design.

Figure 4.38: Device pricing.

62



5
Conclusion

5.1 Results from present work

The target of this thesis work is fulfilled successfully. The OBC and DC-DC converter
topology are selected, implemented and simulated with the software LTspice. The topology
performance is also investigated. In general, the switching pattern of ZVS and phase shift
control strategy is well applied to control the MOSFETs for OBC and DC-DC. The switching
losses and noise is greatly decreased. To be specific,

– The dual active bridge is applied on the OBC converter. Power from the grid
will flow through to charge the HV battery. Since the secondary side of this full
bridge is bi-directional, the secondary side will work as the input side of DC-DC
converter to charge the 12V battery.

– The DC-DC functionality is achieved as the full bridge converter uses the needed
components from the DAB secondary side and current doubler with synchronous
rectification. The inductance is selected to lower the current ripple.

– The power losses for each topology is also involved. It meets the original design
target.

The isolated OBC and DC-DC transformer is designed as the reference. To compare, a three
winding transformer structure including the core and winding is introduced and carried out
in detail. It is clearly indicated that the combined three winding transformer could transfer
power for the DC-DC and OBC with approximately the same efficiency. More advanced,
the volume and cost consequences of components are assessed roughly. The results shows
that the dimension is reduced in a big step. Hence it is feasible to combine the OBC and the
DC-DC converter design in one package to enhance the power density.

5.2 Future Work

To continue with this thesis work, a few topics could be carried out:

– Replace MOSFITs with alternative semiconductors devices in simulations, i.e.
GaN and SiC

– Design the dynamic controller to control and drive the MOSFET gate signal.

63



Chapter 5. Conclusion

– Design and test a PCB board and verify the simulated results on the real converter.

– Investigate the converter’s performance in different working loads as well as for
different frequencies .

– The insulation of AC charger during driving mode and the isolation of DC-DC
converter during grid charging mode need to be solved by suitable control.

64



References

[1] PK.Jain," Power Electronics for Low Voltge Semiconductor Technology: Chal-
lenges and Some Possible Solutions," Proc.of Power Electronics and Motion
Control Conf.(IPEMC’04),2014,pp.20-28

[2] M. H. Kheraluwala, R. W. Gascoigne, D. M. Divan, and E. D. Bau- mann,
“Performance characterization of a high-power dual active bridge DC-to-DC
converter,” IEEE Transactions on Industry Applications, vol. 28, no. 6, pp.
1294–1301, Nov./Dec. 1992

[3] R. W. A. A. De Doncker, D. M. Divan, and M. H. Kheraluwala, “A three-
phase soft-switched high-power-density DC/DC converter for high-power appli-
cations,” IEEE Transactions on Industry Applications, vol. 27, no. 1, pp. 63–73,
Jan./Feb. 1991

[4] Kim B S, Kim H J, Jin C, et al. A digital controlled DC-DC converter for electric
vehicle applications[C]//Electrical Machines and Systems (ICEMS), 2011 Inter-
national Conference on. IEEE, 2011: 1-5.

[5] PUZINAS A, SADEGHPOUR S. Energy Efficiency Investigation of a 3kW
DC/DC Converter for Electric Vehicle Applications using Full Wave and Cur-
rent Doubler Synchronous Rectification[J].

[6] Power Electronics: Converters, Applications, and Design 3rd Edition by Ned
Mohan (Author), Tore M. Undeland (Author), William P. Robbins (Author)

[7] Chiang, P., Hu, M. Switching Analysis of Synchronous Rectifier MOSFETs
With Phase-Shifted Full-Bridge Converter and Current Doubler. VISHAY SILI-
CONIX, Application Note, 833.

[8] Krismer, Florian. Modeling and optimization of bidirectional dual active
bridge DC-DC converter topologies. Diss. Diss., Eidgenössische Technische
Hochschule ETH Zürich, Nr. 19177, 2010, 2010.

[9] Fundamentals of Power Electronics SECOND EDITION Robert W. Erickson,
Dragan Maksimovic, University of Colorado, Boulder, Colorado

[10] Biao Zhao, Student Member, IEEE, Qiang Song, Member, IEEE, Wenhua Liu,
Member, IEEE and Yandong. SunOverview of Dual-Active-Bridge Isolated Bidi-
rectional DC-DC Converter for High-Frequency-Link Power-Conversion System

[11] PWM Plus Phase-Shift Control For Dual Active Full-Bridge DC-DC Converter

65



References

by Yang Min. Advised by Professor Ruan Xinbo, Nanjing University of Aero-
nautics and Astronautics (Chinese)

66


	Abstract
	Acknowledgements
	Table of Contents
	Abbreviations
	1 Introduction
	1.1 Background
	1.2 Previous work
	1.3 Purpose
	1.4 Sustainability and ethics aspects

	2 Theory
	2.1 Design overview
	2.2 Soft switching - Zero Voltage Switching
	2.3 DC-DC part of OBC
	2.3.1 Switching pattern
	2.3.2 Circuit operation

	2.4 DC-DC
	2.4.1 DC-Dc switching pattern
	2.4.2 Circuit operation

	2.5 Transformer
	2.6 Semiconductor losses determination
	2.6.1 Switching losses
	2.6.2 Conduction losses

	2.7 Topology overview

	3 Case set up
	3.1 Specification
	3.2 Passive components selection
	3.2.1 DC-DC part of OBC resonance inductance selection
	3.2.2 DC-DC Passive components selection

	3.3 Operation frequency
	3.4 Component selection
	3.4.1 Semiconductor selection

	3.5 Transformer design
	3.5.1 Turns ratio determination
	3.5.2 Core Design
	3.5.3 Winding Design


	4 Results and analysis
	4.1 Topology simulation results
	4.1.1 OBC charging path simulation and analysis
	4.1.2 DC-DC topology simulation and analysis

	4.2 Transformer selection
	4.2.1 Turns determination
	4.2.2 Core design
	4.2.2.1 OBC isolated transformer
	4.2.2.2 DC-DC isolated transformer
	4.2.2.3 Three winding transformer

	4.2.3 Winding
	4.2.3.1 OBC transformer
	4.2.3.2 DC-DC transformer
	4.2.3.3 Three winding transformer


	4.3 Semiconductor losses
	4.3.1 Semiconductor losses for OBC
	4.3.2 Semiconductor losses for DC-DC
	4.3.2.1 DcDc full bridge topology semiconductor losses
	4.3.2.2 DC-DC current doubler topology semiconductor losses


	4.4 Efficiency
	4.4.1 Efficiency of OBC path
	4.4.2 Efficiency of DC-DC path

	4.5 Design comparison

	5 Conclusion
	5.1 Results from present work
	5.2 Future Work

	References