Assessing RISC-V Vector Extension for Machine Learning - Hellström, Johan; Ghamlouch, Marwan (My University, 2023)
This report presents a partial design and implementation of a soft RISC-V vector extension on a field-programmable gate array (FPGA) based on the most recent and ratified specification (v1.0), with the aim to investigate the suitability of RISC-V vector processor extensions for machine learning applications. The results were obtained by creating a matrix multiplication benchmarking program compiled in GCC and modifying configurations that altered the behavior of the designed prototype. The configurations that could be altered were vector length and whether or not forwarding from the execute stage was enabled. We also implemented our design in a synthesis tool (Vivado) in order to estimate resource usage, power consumption and timing. From our prototype we were able to find that we could, for our benchmarking program, improve the performance by up to 5.4 relative to a scalar RISC-V processor, but at the cost of a notable resource usage and power increase. In conclusion, we believe that vector extension is suitable for machine learning applications because of the achievable performance increase, however the design should be heavily optimized to reduce the resource utilization to capitalize on this.
Keywords: RISC-V; ISA; ISA extension; vector; processor; machine learning