Comparison of different driver topologies for RF Doherty power amplifiers - Asghari, Zahra (My University, 2015)
This thesis investigates different driver topologies for RF Doherty power amplifiers (DPAs). The investigation is based on the simulation of four different driver configurations in Matlab and Advanced Design Systems (ADS) tools. The topologies of the two-stage PA are as follows: (1) cascaded class-AB and a DPA, (2) two-stage cascaded DPAs, (3) DPA with embedded class-ABs and (4) DPA with embedded Dohertys as drivers. Using ideal transistor models, the analysis of the different two-stage power amplifier topologies have been compared through Matlab simulations. The results show that the two-stage cascaded DPA provide the best performance since its efficiency in back-off is higher than the other topologies. To verify the Matlab simulations, the different topologies have been designed and simulated in ADS using real transistor models. The driver and final-stage designed based on 10W (CGH40010F) and 45W (CGH40045F) GaN-HEMT transistors from Cree devices respectively. The required fundamental source and load impedances are obtained from the source- and load-pull simulations. Moreover, the second and third harmonic terminations have been simulated and tuned in order to get the highest possible Power- Added Efficiency (PAE). These amplifiers have made the basis to simulate the four different two-stage power amplifier efficiencies. The ADS simulation results are in good agreement with the Matlab simulations and confirm that the two-stage cascaded DPAs outperforms the other topologies in term of efficiency. All four different topologies have been designed in band-I (2.11-2.17 GHz). The two-stage cascaded Doherty PA exhibits the highest PAE. It consists of the Doherty driver-stage that exhibits a peak output power of 42dBm, a power gain of 13 dB, a PAE of 60% at 6dB back-off and 74% at peak output power. The Doherty-final-stage has 58% PAE at 6-dB back-off and a peak PAE of 73%. Its power gain and peak output power are 12 dB and 50 dBm, respectively. The simulation results of the two-stage-cascaded DPA provides 26 dB power gain at 50 dBm peak output power, a PAE of 58% at 6-dB back-off and 73% PAE. The desired topology (2) exhibits 3% and 5% more PAE comparing to the topology (1) and (3) at 6-dB output back-off respectively. In addition it has about 3% more PAE comparing to the topology (4) at the peak output power. Regarding to the total gain, topology (1) has the highest gain. However, topology (4) has a very flat gain of 30.5-31.5 dB over Pout = 34-49.5 dBm which can result in a more linear behavior. The obtained results demonstrate the importance of the driver topology on total efficiency of the two-stage power amplifiers when signals with large PAPR are used.
Keywords: Elektroteknik och elektronik; Hållbar utveckling; Telekommunikation; Informations- och kommunikationsteknik; Elektronik; Electrical Engineering, Electronic Engineering, Information Engineering; Sustainable Development; Telecommunications; Information & Communication Technology; Electronics