Examensarbeten för masterexamen // Master Theses
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Browsar Examensarbeten för masterexamen // Master Theses efter Program "Integrated electronic system design, MSc"
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- PostA control system and power electronic for an electric powertrain implemented on a go-kart(2014) Ölund, Andreas; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)This report describes the master thesis project where a 3-phase AC -inverter is designed with software to space vector modulate the output currents. The report outlines a brief background to the project and then goes on to describe the demands that the inverter must ful ll. The controlling software is described both in general and the application speci cs are treated. The hardware solution is described and major component choices are discussed. The complete working inverter was successfully implemented on a go-kart, and the testing veri es that the functionality of the inverter is according to the speci cations. The inverter was not fully tested to the upper limits of 72V and 300V peak current due to lack of testing equipment, though the results are promising for the inverter to be able to handle this. 4
- PostASIC Design of a Low-Noise Low-Cost Ultrasonic Amplifier(2014) Tour Savadkouhi, Mahmoud; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
- PostImplementing a PCI-Express AMBA interface controller on a Spartan6 FPGA(2013) Sakthivel, Anandhavel; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)The Purpose of this Master thesis is to integrate the Xilinx PCI-Express interface core to the GRLIB framework. Xilinx Spartan6 Endpoint block for PCI-EXPRESS is generated using Coregen and integrated with the GRLIB framework. The design accounts for crossing clock domains as it is inevitable in a system of chip design with multiple components running at different frequencies. The implementation satisfies the Specification provided by AMBA and PCI-EXPRESS. The performance and area requirement are taken into consideration and different forms of the design is implemented in order to address it. The communication between PC and GRLIB memory environment and the other way around is performed and verified. Simple C codes are developed in order to initiate transfers and also to verify the design. Debugging tools like GRMON, LSPCI and drivers provided by Xilinx are used for analysing and verifying the design. Using GRMON the PCI-EXPRESS debug environment could transfer data at the rate of 120 Mbits/second from PC to the memory of GRLIB. The complete design work was carried out at Aeroflex Gaisler AB.
- PostInterfacing the Xilinx SP601 Spartan 6 development board to the GRLIB IP library(2013) Winsten, Mattias B; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)This report provides a detailed description of interfacing the developing board "Spartan 6 SP601" with GRLIB's standard IP library. The thesis was carried out at Aeroflex Gaisler at Kungsgatan in Gothenburg. The main part of the thesis consisted of designing a wrapper interfacing the Xilinx Memory Controller Block (MCB) with the Advanced Microcontroller Bus Architecture (AMBA). AMBA is a processor bus architecture developed by ARM for on-chip communication in embedded microcontrollers. GRLIB is a standard IP library (available with GNU General Public License) using AMBA for internal communication. The MCB is a hard circuit within the Xilinx Spartan 6 FPGA that is available through Xilinx's Core Generator software. The MCB is connected to 128MB DDR2 memory provided by Elpida. A board specific template design was created including a Leon 3 processor, AHB controller, IP blocks for reset and clock generation and SPI memory controller, all IP components within GRLIB IP library. During logical simulation a patched SecureIP block from Xilinx was used to simulate the MCB's physical part. The developing language was VHDL (hardware description language), and logical simulation was performed with Modelsim 6.5e. Xilinx ISE developing tools were used for the synthesis and Impact was used downloading the design into the FPGA. Gaisler's GRMON software was used to debug and verify the hardware. Benchmarks and verification was carried out using a set of benchmark programs including Dhrystone and self-developed test software.
- PostUVM Based Verification Of 3GPP Chip Rate Processing Unit(2013) Mahaveer Anadka, Abeesh; Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers); Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)Exchange of information in the present world has witnessed a significant progress owing to modern telecommunication technologies, advanced gadgets and powerful computers. Wireless networks are the most popular choice for the obvious reason of connecting people on the move. Cellular technology provides a wide area connectivity and potential of generating higher revenues to the service provider. Universal Mobile Telecommunication System (UMTS) is a 3rd Generation (3G) technology that offers a high speed data access besides conventional voice service. 3rd Generation Partnership Project (3GPP) committee defines the standards for UMTS technology. UMTS uses Wideband Code Division Multiple Access (WCDMA) for radio transmission. A cellular network infrastructure houses an access point termed as base station to enable radio connectivity to the mobile devices. The base station hardware requires validation to determine its performance and limitation. Specialized hardware is used by Ericsson for testing baseband processing of base station which can emulate multiple mobile terminals. This hardware resembles a Real-time User Equipment (RUE) which is capable of simulating different scenarios of wireless transmission and modes of mobile devices. This test infrastructure encapsulates Digital Signal Processors (DSPs), Field- Programmable Gate Arrays (FPGAs) and other components. One FPGA is used for generating the data needed for transmission to the base station. FPGA performs the physical layer chip rate processing where all the information carrying data and control signals are represented in radio frames. The purpose of this thesis is formal verification of this FPGA based on Hardware Description Language (HDL) simulator. Specman is a Cadence tool used to create test benches for verifying FPGA and executes the test cases along with a HDL simulator. It provides a standard for defining, compiling and executing a test environment developed in e language. This project uses Specman based verification of the uplink chip rate processing of the FPGA which includes many unit level signal processing blocks. The test bench autonomously generates the necessary inputs, predicts the output using a reference model, monitors the outputs and compares it with predicted output. The sequence of generation of inputs is designed to simulate specific cases defined in 3GPP specification. The device timing, control and configuration information needed is precisely included in test environment. The test results are summarized with coverage information on different combination of inputs tested or occurrence of certain events.