Class D Power Amplifier Design in 22nm CMOS for RF delta-sigma Modulated Signals

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/301425
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Type: Examensarbete för masterexamen
Title: Class D Power Amplifier Design in 22nm CMOS for RF delta-sigma Modulated Signals
Authors: Langborn, Björn
Abstract: For future communication and sensor systems, energy efficient transmitters are essential to achieve good system performance. To this end, this thesis has investigated the efficiency, frequency, power and bandwidth limitations of Class D power amplifiers for bandpass delta-sigma modulated signals. Herein, bandpass delta-sigma modulation (BPDSM) allows for digitization of analog information signals, which is attractive from a system perspective, whereas Class D power amplifiers are suitable for digital signals and has an ideal efficiency of 100%. This paper will begin with theory on delta-sigma modulation, choice of semiconductor process technology, amplifier topology, and operational and design principles. From this theory, design equations are found that determine the limitations on the achievable output power and drain efficiency. Key parameters for the BPDSM and class D stage are highlighted. Three loss mechanisms for the class D stage are identified and quantified, namely switching, conduction and short circuit losses. Simulation studies have been performed, for the circuit in Cadence’s Virtuoso Analog Design Environment (CVADE) using GlobalFoundries 22nm FDSOI CMOS technology, and for the BPDSM in MATLAB using R. Schreier’s Delta Sigma Toolbox. The simulations in CVADE were performed using Super Low-Voltage Threshold (SLVT) transistors. These simulations included transistor characterization by DC and S-parameter simulations, and circuit performance comparison between a class D stage using SLVT transistors with a switch model class D stage. From the design equations, the output power is seen to be limited by the BPDSM coding efficiency eta-c, transistor on-resistances Ron and the process technology limiting the drain voltage VDD. Furthermore, it is suggested that both the output power PL and the drain efficiency eta-d will be especially limited by high Ron, resulting in conduction loss, if the class D transistor widths are small. On the other hand, large transistor widths are expected to yield dominant switching losses at higher frequencies, due to parasitic capacitances, thus reducing eta-d. The oversampling ratio Rc = fs/(2fc) of the BPDSM is determined a key performance factor, because of its impact on both Rc and the switching losses. These theoretical results are confirmed in simulations. Additionally, it is found that eta--c is limited by the input signal peak amplitude and Peak-to-Average Ratio (PAR), for signal preservation through the BPDSM and class D stage. However, no conclusive bandwidth limitation of the BPDSM class D PA is found in this study. Approaches to address the respective limitations, and alternative topologies that could improve performance, are mentioned.
Issue Date: 2020
Publisher: Chalmers tekniska högskola / Institutionen för mikroteknologi och nanovetenskap (MC2)
URI: https://hdl.handle.net/20.500.12380/301425
Collection:Examensarbeten för masterexamen // Master Theses



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