S Band Multi-function Down-converter GaAs MMIC

Abstract

An S band, high-linearity down-converter is implemented using a 0.25 um GaAs MMIC pHEMT-process. Using UMS' PPH25 process, an unbalanced FET resistive mixer with a lumped diplexer and an integrated square-wave LO-drive performs the down-converting. The produced narrowband IF-signal is then amplified twice, first in an LNA and then in a highly linear amplifier. The chip has a dynamic gain variation of 10.5 dB and offers a maximum gain of 15 dB. The input 1 dB-compression point at nominal gain is 10 dBm which estimates input IP3 to 20 dBm. The noise figure at nominal gain is 11 dB. The chip offers down-converting of RF-frequencies between 2.9 and 3.4 GHz for input LO-signals of -4 - 0 dBm and an image rejection of 40 dBc. The chip size is 2.4×3.4 mm, and it is designed to fit in a 4×5mm QFN-capsule and consumes 1.0W of DC power. Three control signals govern the dynamic attenuation with an LSB of 1.6 dB. Comparative studies regarding mixer topologies and process technologies are performed. The choice of a single cold FET resistive mixer type is motivated by its linearity, small size and simplicity. A medium-power pHEMT process is chosen, as this provides improved linearity of the amplifiers as well as acceptable noise features given the requirements.