Custom precision floating-point implementation of BAPS algorithm for hardware-efficient digital predistortion

Abstract

Modern wireless communication systems demand improved spectral efficiency and power conservation, placing stringent requirements on radio frequency power amplifiers. Digital predistortion (DPD) techniques linearize power amplifiers while enabling efficient operation, with the basis-propagating selection (BAPS) algorithm offering computational efficiency through systematic reuse of basis functions. However, hardware implementation of BAPS remains underexplored, particularly regarding floating-point precision requirements that impact both linearization performance and hardware resource utilization. This thesis systematically investigates floating-point precision requirements for BAPSbased DPD digital circuit implementations through analysis of 40 custom precision configurations spanning mantissa widths from 5 to 23 bits and exponent widths from 5 to 8 bits. A precision-configurable hardware architecture using parameterizable VHDL with Cadence ChipWare floating-point IP enables rigorous evaluation across four distinct BAPS configurations. Results demonstrate that mantissa width critically determines performance, with 9- bit mantissa maintaining robust operation and 7 bits representing a critical threshold for degradation, while exponent width can be aggressively reduced from 8 to 5 bits without performance penalty. Hardware complexity analysis reveals approximately linear scaling with mantissa width, with a balanced configuration achieving 80% area reduction while maintaining linearization performance within 0.4 dB of single precision. These findings enable substantial hardware efficiency improvements for DPD implementations in resource-constrained 5G and emerging 6G wireless systems while maintaining required linearization performance.