Precision Exploration and Underflow Mitigation for BAPS Digital Predistortion

Abstract

Digital predistortion (DPD) is widely used to compensate for the nonlinear be haviour of radio-frequency power amplifiers (PAs). The basis-propagating selection (BAPS) algorithm builds DPD models by reusing previously computed basis functions, making it attractive for hardware implementation. However, when reduced precision floating-point arithmetic is used, these sequential multiplication chains create dynamic range challenges. This thesis investigates how the number of mantissa bits (t), the number of exponent bits (w), and the number of BAPS basis functions (R) affect DPD linearisation performance, evaluated using normalised mean square error (NMSE) and adjacent channel power ratio (ACPR), and hardware cost. A Python-based simulation framework using the APyTypes library is developed to evaluate custom floating-point configurations and generate test vectors for register-transfer-level (RTL) verification. A joint sweep of R and t produces a two dimensional NMSE heatmap. For the selected BAPS sequence and test case, the performance plateau is reached at R = 6 and t = 7; larger values give no measurable NMSE improvement. This extends the fixed-R mantissa-width result reported in prior work by showing the joint effect of R and t. Reducing t from 23 to 7 reduces the synthesised area by approximately 78% without measurable loss in DPD linearisation performance. The exponent-width study shows that, without scaling, intermediate Type II products underflow at w = 5, removing important basis functions and making the predistorter ineffective. This thesis therefore uses power-of-two scaling, which raises these products using exponent shifts only, without additional floating-point multipliers. At t = 7, the scaled (w,t) = (5,7) design recovers performance close to the reference level and uses 5.9% less area than the scaled (6,7) design. At w = 4, the model coefficients underflow, so w = 5 is the practical lower bound for the studied signal and PA operating point. The configuration (w,t) = (5,7) with power-of-two scaling reduces the synthesised total area to 21% of the single-precision baseline, while meeting the common 5 ns clock-period constraint used for the synthesis of all configurations, including the single-precision baseline. Selected configurations are also validated using the RF WebLab measurement platform and PA gate-voltage robustness tests. The results show that reduced-precision BAPS DPD can provide substantial hardware savings while maintaining linearisation performance close to the full-precision reference.