ML-based power analysis for ASIC IP development
dc.contributor.author | Liu, Wei | |
dc.contributor.department | Chalmers tekniska högskola / Institutionen för mikroteknologi och nanovetenskap (MC2) | sv |
dc.contributor.department | Chalmers University of Technology / Department of Microtechnology and Nanoscience (MC2) | en |
dc.contributor.examiner | Peterson, Lena | |
dc.contributor.supervisor | Larsson-Edefors, Per | |
dc.date.accessioned | 2025-07-04T04:21:48Z | |
dc.date.issued | 2025 | |
dc.date.submitted | ||
dc.description.abstract | Accurately estimating power consumption is critical for designing Application-Specific Integrated Circuits (ASICs), especially as they grow more complex. This thesis investigates the application of machine learning (ML) for ASIC power analysis. We establish a comprehensive flow encompassing dataset generation and power simulation. Subsequently, we develop and evaluate several ML models, categorized as architecture-based and flow-based approaches. Our findings reveal varying degrees of success among these models, with some demonstrating strong predictive capabilities while others exhibit limitations. Finally, we propose potential avenues for future research to address the identified challenges and further enhance the accuracy of ML-based power prediction. | |
dc.identifier.coursecode | MCCX04 | |
dc.identifier.uri | http://hdl.handle.net/20.500.12380/309945 | |
dc.language.iso | eng | |
dc.setspec.uppsok | PhysicsChemistryMaths | |
dc.subject | Machine Learning, ASIC Power consumption | |
dc.title | ML-based power analysis for ASIC IP development | |
dc.type.degree | Examensarbete för masterexamen | sv |
dc.type.degree | Master's Thesis | en |
dc.type.uppsok | H | |
local.programme | Embedded electronic system design (MPEES), MSc |
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