Numerical Simulations of Device Scaling of a Pseudomorphic InP HEMT

Abstract

A Technology CAD (TCAD) model of a pseudomorphic indium phosphide high electron mobility transistor (HEMT) optimized for cryogenic operation has been developed. The model has been used to investigate the prospects of improving the radio frequency performance of the device by means of device scaling, specifically through the scaling of the gate length and the distance between the gate electrode and the channel. The model describes the movement of charge carriers within the HEMT structure using an isothermal transport model, where carrier velocities are limited by phonon scattering and high-field velocity saturation. The undesired transport of electrons from the gate electrode into the channel is accounted for through the modeling of thermionic emission and quantum tunneling. The lateral scaling of the device model suggests that advantages such as a 92 % increase of the unity current gain cut-off- frequency fT can be achieved by reducing the gate length from its original 130 nm to 10 nm. Scaling of the gate-channel separation from 11 nm to 8 nm was attempted as a measure to reduce the impact of various short-channel effects (SCEs), but was found to be insufficient. A drastically lowered peak transconductance and threshold voltage at gate lengths below 70 nm suggests that further engineering of the HEMT structure is necessary in order to mitigate the SCEs and to improve the small-signal power gain. Proper dimensions for future transistor designs are ultimately decided by requirements in terms of the optimal low-noise bias point and the suppression of leakage currents.