A Fast Wafer-Level Reliability Study of Multi-Time Programmable (MTP) Memory Devices

Abstract

The task of this project was to devise a method for fast wafer level reliability testing of non-volatile memories for process development and qualification, in both siliconon-insulator (SOI) as well as CMOS bulk substrate technologies, with an aim to engineer out the conventional wafer baking step using an oven, thus, reducing the time and cost for reliability testing. This master thesis has been written during my internship in the reliability group of the front-end innovation department at NXP Semiconductors, Nijmegen, The Netherlands. The thesis report is divided into the following chapters. - Chapter 2 provides a basic overview of the types of non volatile memories relevant to this thesis - Chapter 3 is dedicated to multi-time programmable (MTP) memories; the device under study in this thesis project - Chapter 4 concerns the existing design for fast Wafer Level Reliability testing of MTP (fWLR-MTP) memory devices. - Chapter 5 discusses the thermal simulations performed on the existing 3-finger fWLR-MTP test structure using the COMSOL Multiphysics environment. - Chapter 6 focuses on the improvement of the existing fWLR MTP design to meet the project goals i.e. a temperature of 250 oC in the MTP device region. Also, the designs of the layout for the improved designs, which were sent for fabrication, are presented in this chapter. - Chapter 7 presents a summary of the project and also discusses the future impact of it.