Real-time Target Detection Using a CFAR Feature Plane in an Embedded System

Abstract

Technologically advanced weapon systems – such as drones and high-precision ballistic missiles – have become defining features of modern warfare. This development has increased the demand for radar systems capable of detecting threats quickly and accurately, even in dynamic and cluttered environments, while maintaining a constant false-alarm rate (CFAR) independent of the interference model. In such settings, signal mismatches between expected and measured target steering vectors are common, requiring detectors that can be tuned for desired selectivity or robustness. The CFAR Feature Plane (CFAR-FP) is a recently proposed method for evaluating different CFAR detectors. It maps radar echoes to a two-dimensional feature space using invariant detection principles, forming distinct groups of clusters for the target and noise hypotheses. Within this plane, traditional CFAR detectors appear as linear or non-linear decision boundaries that separate the clusters depending on the desired selectivity or robustness. However, in scenarios with low signal-tonoise ratio (SNR) or significant signal mismatches, these detectors may suffer from degraded performance. To address this issue, a neural network (NN) can be used as a binary classifier to learn complex and data-driven detection thresholds, which otherwise would not be possible with traditional detectors. This thesis explores the design and implementation of a robust and tunable CFAR detector based on the CFAR-FP framework and an NN directly in the Xilinx Versal AI core series VCK190 FPGA. The board’s combination of reconfigurable logic and embedded AI engines (AIE) has the potential of greatly accelerating NN-based classification in real time, making it a viable candidate for edge AI applications. A complete system model was developed in software, including a MATLAB program for generating the CFAR-FP with customizable target injections into experimental radar data, and an NN model implemented in Python. Experimental results demonstrate that quantizing the NN for deployment on resource-constrained platforms – such as the VCK190 – significantly improves inference speed, albeit with a reduction in prediction accuracy on highly mismatched and low SNR datasets. In parallel, VHDL-based modules have been developed for executing advanced complex-valued linear algebra operations required by the CFAR-FP mapping chain on an FPGA. The results show that a fully pipelined hardware implementation – from processing chain to NN inference – is feasible, enabling high-speed signal processing and detections at the cost of higher design complexity and loss in computational precision.