Verification and performance evaluation methodologies for open-source SoCs on FPGA proof-of-concept platforms

Abstract

Verifying functional correctness and evaluating performance before committing a design to silicon is a resource-limited challenge, particularly for academic groups and small enterprises lacking access to large-scale simulation infrastructure or proprietary IP. This thesis proposes a methodology for functional verification and performance monitoring using open-source SoC platforms (as they are free) to build a proof-of-concept prototype to test it on an FPGA (as they are cheap and accessible). It combines a staged flow with a top-down performance modelling approach in which fine-grained hardware counter instrumentation is added only where an abstract model identifies a bottleneck. The methodology is evaluated through a case study on the open-source Pulpissimo platform, ported to a previously unsupported FPGA target (KCU105 board from AMD), across a single-core baseline and the same system augmented with a hardware MAC accelerator. For each system, an execution-time model adapted from the literature is mapped onto existing and newly-designed hardware counters, integrated into the platform’s RTL, and verified in simulation before being validated on FPGA. The baseline model reproduces measured execution time within 11%, using instrumentation that costs under 2% of on-chip logic area. For the accelerator-augmented system, the model was extended to capture dispatch overhead that scales with offload granularity. Both models correctly attribute the dominant performance bottleneck: core-internal effects for the baseline, and SoC-integration effects once the accelerator is added. This instrumentation was possible because the platform is open-source: its RTL could be directly modified to add the required counters, which is not generally achievable with proprietary IP. Together, these results demonstrate a low-overhead, adaptable modelling methodology suited to the resource constraints faced by academic groups and small enterprises.