Design of complex multiply-accumulate RISC-V extension for accelerating quantum simulations

Abstract

Quantum circuit simulation is an important tool for developing and testing quantum algorithms, but its computational and memory requirements grow exponentially with the number of qubits. A significant part of the computational workload consists of complex-valued matrix–vector operations. Depending on the circuit, the corresponding unitary matrices may contain many zero-valued coefficients that do not contribute to the result. This thesis investigates whether such sparsity can be exploited using specialized hardware. A preliminary analysis of representative quantum circuits was performed to examine the sparsity of their unitary matrices. Based on this motivation, a complex sparse matrix-vector multiplication (SpMV) accelerator was developed using the compressed sparse row (CSR) representation. The architecture consists of vector permutation, parallel complex multiplication, and row accumulation stages. It is intended for use as a coprocessor within an X-HEEP RISC-V system, although the present evaluation considers the standalone accelerator. The accelerator was verified through RTL simulation and synthesized using Cadence Genus with the ASAP7 technology library. Synthetic 8 × 8 complex matrix tiles with densities between 9.4% and 100% were used for evaluation. Timing closure was demonstrated at up to 440 MHz. Reducing the number of non-zero coefficients from 64 to 6 decreased the execution time from 129 to 21 clock cycles, corresponding to a speedup of approximately 6.14× relative to a 100%-dense tile processed by the same accelerator. At 440 MHz, the estimated energy per tile-level operation was reduced by approximately 74%. These results demonstrate that the proposed architecture can exploit matrix sparsity to reduce tile-level execution latency and estimated energy. Complete processor integration and end-to-end quantum-simulation performance remain subjects for future evaluation.