Analysis and improvement of phase noise performance of a PLL-based RF synthesizer

Abstract

The goal of this thesis work was to analyze, model and improve the phase noise performance of a wideband synthesizer prototype. The analyzed synthesizer is based on a phase-locked loop (PLL) with an active loop filter, where the output frequency range is 2340MHz − 4420MHz in steps of 260MHz. The noise analysis carried out in the thesis places emphasis on the loop filter and proposes a model for a model for simulation of phase noise at the output of the PLL. The model is verified through measurements and a new filter design is proposed. The new filter is designed for reduced thermal noise which reduces the PLL output phase noise. At an output frequency 3120MHz, the simulated phase noise of the synthesizer with the new filter design is −124.4 dBc/Hz at offset frequency 1MHz, which is an improvement of more than 7.5 dB compared to the synthesizer with the original filter design.