W-Band Power Amplifier Design

Abstract

This thesis presents two W-band power amplifiers (PA) in different processes: one is Teledyne 250 nm indium phosphide (InP) double-hetero-junction bipolar transistor (DHBT) process, and the other is United Monolithic Semiconductors (UMS) 0.1 µm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process. Different power combining topologies are investigated in these two designs. The bandwidth of the interstage matching network is improved by a three-section quarter-wave transformer. In the UMS 0.1 um GaAs pHEMT process, a three-stage PA is designed. Four 40 µm gate-width transistors, each with six fingers, are paralleled by a planar spatial power combiner at the output stage to improve the output power of the PA. The maximum gain of the PA is 14 dB. The 1 dB gain compression point (P1dB) is 21.2 dBm with 14.5% peak power added efficiency (PAE). In the Teledyne 250 nm InP DHBT process, a two-stage power amplifier is implemented. Sixteen four-finger transistors of 10 µm emitter-length are paralleled at both input and output stages to improve the P1dB. The gain of the PA is 12 dB. The P1dB is 23.8 dBm with 11.5% peak PAE. The two circuits are designed in Agilent Advanced Design System (ADS) with transistor and capacitor models offered by the foundries. Transmission line networks for impedance matching, power combining and power splitting are simulated in Momentum, a 2.5-D electromagnetic (EM) software.