Sloppy selection networks for fast energy-efficient decoding

Abstract

This thesis investigates the possibility of reducing the impact of hardware constraints of decoder implementations employing modern soft-decision decoding schemes such as ORBGRAND, GRAND, and Chase-class algorithms for FEC. Sorting networks constitute a major hardware bottleneck in the implementation of such decoders due to their area, power, and delay requirements. To address this problem, sloppy selection is explored as an alternative to conventional sorting, and a generalized architecture for implementing sloppy selection networks is proposed. The proposed architecture provides a configurable trade-off between selection “sloppiness” and hardware complexity. The proposed sloppy selection networks demonstrate a slight degradation in decoding performance while showcasing significant reductions in impact on hardware constraints, achieving up to 96% reduction in area and power consumption, along with up to 80% reduction in delay compared to conventional sorting-based implementations. Furthermore, an MSB-first comparator architecture was introduced to further optimize the comparator logic within the sloppy selection networks. The proposed comparator achieved an additional reduction of approximately 70% in delay and nearly 90% reduction in EDP, while incurring only a modest area increase of approximately 25%. The obtained results strongly indicate the viability of the proposed sloppy selection networks for practical decoder implementations. If comparable decoding performance can be achieved relative to implementations using accurate sorting networks, the proposed architectures could have a significant impact on the design of 5G and 6G decoder hardware.