FPGA-based platform architecture for a distributed MIMO (D-MIMO) 6G testbed

Abstract

A distributed MIMO (D-MIMO) testbed changes shape as the experiments running on it change. On a conventional FPGA, replacing one accelerator means rebuilding and reprogramming the whole device, which takes the shared platform out of service for everybody. This thesis builds a Dynamic Function eXchange (DFX) platform for the ALINX Z19 board and its AMD Zynq UltraScale+ XCZU19EG, in which three regions of the fabric can be replaced independently while the rest of the design keeps running. The static design holds the processing system, the DDR and network paths, three AXI DMA engines, the DFX Controller and the ICAPE3 configuration primitive. Around it sit three reconfigurable partitions that share one boundary contract: a 100MHz clock, an active-low reset, a 32 bit control word, a 32 bit status word, a 32 bit AXI4-Stream port in each direction and a shutdown handshake. Because the three partitions present the same 146 pins, a module is written once; because they sit in different places on the die, it is built once per partition against that partition’s abstract shell. An accelerator developer therefore needs neither the parent project nor its bitstream: a routed shell, one 1.75MB checkpoint per partition, and their own VHDL are enough. A standalone application on the Cortex-A53 serves a browser console and an HTTP API over lwIP. Uploading a partial bitstream to a slot validates it against the device IDCODE and the partition’s own configuration frame address, hands the configuration port from PCAP to ICAPE3, and drives the virtual socket manager through shutdown, address programming, restart and trigger. The implemented design closes timing with +4.342 ns of setup slack against 10 ns period with no failing endpoints and no unrouted nets, and it occupies 2.31% of the device LUTs, 1.66% of its registers and 0.61% of its block RAM. It produced a 3.63 kB full bitstream and three partials of 2.59–3.19MB, whose sizes track partition geometry rather than module content. At the 96.97MHz PL clock recorded in the hardware handoff and the 32 bit ICAPE3 port, their ideal configuration-transfer times are 6.69–8.23ms against 93.70ms for the full image. Hardware validation exposed four problems not revealed by reports or simulation: ICAPE3 required software to transfer ownership of the configuration interface from PCAP; the unsupported Ethernet PHY required explicit RGMII skew programming; link speed had to be read after negotiation; and enabled but unused transceiver peripherals could stall processor initialisation and JTAG until the board was powercycled. After these corrections, the board boots unattended, answers ping in 110ms and reconfigures any partition over HTTP while the other two continue running. D-MIMO physical-layer accelerators remain future work.