Logic Gates Switching Harmonics

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/125612
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Type: Examensarbete för masterexamen
Master Thesis
Title: Logic Gates Switching Harmonics
Authors: Khan, Muhammad Imran
Abstract: This report deals with the study of spectrum generation from logic circuits, in order to better understand how to suppress the generation of high harmonics, especially in a given frequency band. It is well known that signals with fast edges contain more energy at higherfrequency spectral components [3]. However, existing closed-form expressions become increasing unwieldy to cover high order harmonics (10th harmonic and above) [1]. Furthermore, circuit simulations of such waveforms are difficult, and certain insights are needed to correctly interpret the simulation results. For tool setup simulations of simple inverter were performed with Cadence Spectre simulator using 65 nm and 130 nm process technologies and data points were transferred to Matlab to plot the FFT spectrum of switching waveforms. Three different flip-flop structures PowerPC 603 Master-Slave Latch, modified C²MOS Latch, hybrid-latch flip flop (HLFF) were also designed and simulated using 130nm process technology. Comparison between three flip flop structures was also done in terms of time delay, power dissipation and FFT spectrums of switching waveforms. Performance of hybridlatch flip flop (HLFF) was best as compared to other two structures
Keywords: Datorteknik;Computer Engineering
Issue Date: 2010
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/125612
Collection:Examensarbeten för masterexamen // Master Theses

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