UVM Based Verification Of 3GPP Chip Rate Processing Unit

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/176640
Download file(s):
File Description SizeFormat 
176640.pdfFulltext3.52 MBAdobe PDFView/Open
Type: Examensarbete för masterexamen
Master Thesis
Title: UVM Based Verification Of 3GPP Chip Rate Processing Unit
Authors: Mahaveer Anadka, Abeesh
Abstract: Exchange of information in the present world has witnessed a significant progress owing to modern telecommunication technologies, advanced gadgets and powerful computers. Wireless networks are the most popular choice for the obvious reason of connecting people on the move. Cellular technology provides a wide area connectivity and potential of generating higher revenues to the service provider. Universal Mobile Telecommunication System (UMTS) is a 3rd Generation (3G) technology that offers a high speed data access besides conventional voice service. 3rd Generation Partnership Project (3GPP) committee defines the standards for UMTS technology. UMTS uses Wideband Code Division Multiple Access (WCDMA) for radio transmission. A cellular network infrastructure houses an access point termed as base station to enable radio connectivity to the mobile devices. The base station hardware requires validation to determine its performance and limitation. Specialized hardware is used by Ericsson for testing baseband processing of base station which can emulate multiple mobile terminals. This hardware resembles a Real-time User Equipment (RUE) which is capable of simulating different scenarios of wireless transmission and modes of mobile devices. This test infrastructure encapsulates Digital Signal Processors (DSPs), Field- Programmable Gate Arrays (FPGAs) and other components. One FPGA is used for generating the data needed for transmission to the base station. FPGA performs the physical layer chip rate processing where all the information carrying data and control signals are represented in radio frames. The purpose of this thesis is formal verification of this FPGA based on Hardware Description Language (HDL) simulator. Specman is a Cadence tool used to create test benches for verifying FPGA and executes the test cases along with a HDL simulator. It provides a standard for defining, compiling and executing a test environment developed in e language. This project uses Specman based verification of the uplink chip rate processing of the FPGA which includes many unit level signal processing blocks. The test bench autonomously generates the necessary inputs, predicts the output using a reference model, monitors the outputs and compares it with predicted output. The sequence of generation of inputs is designed to simulate specific cases defined in 3GPP specification. The device timing, control and configuration information needed is precisely included in test environment. The test results are summarized with coverage information on different combination of inputs tested or occurrence of certain events.
Keywords: Data- och informationsvetenskap;Computer and Information Science
Issue Date: 2013
Publisher: Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)
Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers)
URI: https://hdl.handle.net/20.500.12380/176640
Collection:Examensarbeten för masterexamen // Master Theses

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.