PLL Design at 5.8 GHz

Examensarbete för masterexamen

Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12380/22820
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Type: Examensarbete för masterexamen
Master Thesis
Title: PLL Design at 5.8 GHz
Authors: Banik, Biddut
Abstract: PLL (Phase Locked Loop) with low phase noise is a prerequisite for a communication system. Besides serving the general purposes as in cell phones, PLL is used in the ISM Bands for other special purposes incorporated with other devices. A double-PLL, generates two signals, at the ISM Band 5.8 GHz can be used for many purposes. ETC (Electronic Toll Collection), Traffic Control, thickness measurement are some examples that use ISM bands. The project s aim is to investigate and design a Double PLL at 5.8 GHz which can be used as a part of the system that would measure the thickness of slag in an Iron furnace. Further investigation and design should take place as per necessity. The components used, should hold pronounced commercial perspectives and availability. Based on the investigation results, proper components were selected to design a Single PLL at 5.8 GHz which was followed by a Double PLL at 5.8 GHz. Further investigations were conducted to attain information about commercially available VCOs, followed by a feasibility study of the commercial perspectives. Detailed considerations regarding VCOs led to the way to design VCOs at 5.8 GHz and 9.9 GHz.
Keywords: Elektronisk mät- och apparatteknik;Övrig elektroteknik, elektronik och fotonik;Electronic measurement and instrumentation;Other electrical engineering, electronics and photonics
Issue Date: 2003
Publisher: Chalmers tekniska högskola / Institutionen för mikroteknologi och nanovetenskap
Chalmers University of Technology / Department of Microtechnology and Nanoscience
URI: https://hdl.handle.net/20.500.12380/22820
Collection:Examensarbeten för masterexamen // Master Theses



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