A Universal-Verification-Methodology- Based Verification Strategy for High-Level Synthesis Design
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Typ
Examensarbete för masterexamen
Program
Embedded electronic system design (MPEES), MSc
Publicerad
2022
Författare
Shen, Haonan
Zhong, Chi
Modellbyggare
Tidskriftstitel
ISSN
Volymtitel
Utgivare
Sammanfattning
High-level synthesis (HLS) enables automatic translation from high-level language
code to register transfer level (RTL) code, which could be a potential method
to improve the development efficiency for hardware design. However, a different
verification flow should be introduced to guarantee the HLS design fulfills design
specifications. The purpose of this thesis is to explore and develop a new
universal-verification-methodology-based (UVM-based) verification workflow particularly
for HLS design. A universal strategy is developed in two different vendors’
tools, Cadence Incisive™/Xcelium™ and Siemens Mentor Graphics QuestaSim
™/Visualizer™, including automatic scripts and highly-reusable code to verify
the HLS C++ design and the HLS RTL design generated by Siemens Mentor
Catapult™. The design under test is a complex 5G communication block design
from Ericsson. We first investigated the existing Cadence-based UVM verification
environment, and updated the current flow into an HLS-specialized flow. Then,
we explored how the verification strategy is realized with Cadence tools including
Incisive/Xcelium. After that, we developed an entire flow in Siemens Mentor
Graphics environment, by migrating the existing UVM verification environment
architecture with Siemens Mentor Graphics supported libraries and developed the
automation process for compilation, optimization and simulation in Siemens Mentor
QuestaSim/Visualizer. Furthermore, to test the feasibility of the Siemens Mentor
Graphics flow we designed, the flow is applied to collect results of functional coverage
and code coverage of an Ericsson’s IP block. In the process of reaching coverage
closure, the intermediate results indicate the demands of developing a series of additional
direct tests, and suggest potential changes in the test plan for regression
test. Finally, based on results in practicing the HLS verification flow in Cadence
and Siemens Mentor Graphics environment, summarized suggestions are given to
Ericsson for further improvements in the HLS verification flow.
Beskrivning
Ämne/nyckelord
High-level synthesis , UVM , IP verification , Multi-language verification