GRLIB Interface to Hard FPGA Subsystems A GRLIB Template Design for the Terasic SoCKit Board

Abstract

Many FPGA vendors implement hard subsystems in their FPGAs, such as the Xilinx Zynq-7000 SoC, and the Altera Cyclone V SoC. A common trait for several SoC FPGAs is that they have AXI interfaces in the interconnect between the hard subsystem and the FPGA fabric. Cobham Gaisler develops and supports the VHDL IP library GRLIB, and want to be able to interface GRLIB to such hard subsystems. This Master of Science thesis describes the implementation of a GRLIB template design for the Altera Cyclone V SoC FPGA, on the Terasic SoCKit board. The design demonstrates how GRLIB can be connected to a hard subsystem, in this case the Altera HPS, using the AXI available interfaces. The template design runs at a clock frequency 70 MHz, and includes a LEON3 processor, as well as several other GRLIB IP cores. An existing AHB-to-AXI bridge was modi ed, and a new AXI-to-AHB bridge was developed to connect the GRLIB AHB bus to thehard subsystem AXI interfaces. The project was executed and successfully veri ed at Cobham Gaisler.