Integrated Circuit Yield Enhancement - Redundant Multi Core DSP Cluster
| dc.contributor.author | Andersson, Mikael | |
| dc.contributor.department | Chalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers) | sv |
| dc.contributor.department | Chalmers University of Technology / Department of Computer Science and Engineering (Chalmers) | en |
| dc.date.accessioned | 2019-07-03T12:27:07Z | |
| dc.date.available | 2019-07-03T12:27:07Z | |
| dc.date.issued | 2010 | |
| dc.description.abstract | The manufacturing of integrated circuits is not a perfect fault-free process. The constant downscaling of integrated circuits requiring higher accuracy each generation also allows the designer to fit more transistors in the same area. From a manufacturing point of view, this downscaling introduces additional possible sources of error, which forces a constant struggle to keep the yield or ratio of successfully manufactured chips high enough to be profitable. The manufacturing success ratio, or yield, is a major component of what determines the time and material cost it takes to manufacture an integrated circuit. To increase yield a common approach is to add redundant or spare parts to the system requiring only enough of them to work. Redundancy has long been a common concept in memories. For random logic blocks, the overhead cost has been too large to be reasonable. But for multi core systems, with several instances of the same logic block, the situation is starting to resemble the case of a memory. The manufacturing yield can be predicted by statistical models. Such models may consist of analytical expressions based on very low level information such as the exact layout features of every transistor and wire of the entire chip. However the addition of a spare core for a multi core cluster is an architectural decision that has to be made in the early stages of the design where low level details are not readily available. The modeling approach taken in this project uses a collection of simplified models previously used for yield calculations for memories. The model results in estimates of the yield before and after the addition of redundant cores. The input parameters to the model are based on gate counts and global routing estimates of an early floor plan together with information about the manufacturing process in the form a fault density. When sources of defects are found and suppressed, the yield ramps up. The yield model presented here also shows the effect the redundancy has on the yield ramp, pushing it towards an earlier volume production date, potentially decreasing the product time to market. | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12380/126773 | |
| dc.language.iso | eng | |
| dc.setspec.uppsok | Technology | |
| dc.subject | Datorteknik | |
| dc.subject | Computer Engineering | |
| dc.title | Integrated Circuit Yield Enhancement - Redundant Multi Core DSP Cluster | |
| dc.type.degree | Examensarbete för masterexamen | sv |
| dc.type.degree | Master Thesis | en |
| dc.type.uppsok | H |
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