Developing a LEON3 template design for the Altera Cyclone-II DE2 board

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dc.contributor.authorBengtsson, Daniel
dc.contributor.authorFång, Richard
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T12:40:00Z
dc.date.available2019-07-03T12:40:00Z
dc.date.issued2011
dc.description.abstractThis Master of Science thesis describes the development of a LEON3 template design for the Altera Cyclone-II DE2 board. A template design is mainly a LEON3 processor system modified to suit a specific board. An existing template design was modified, supporting most of the components on the board. However, the on-board SDRAM circuit has a data bus width of 16-bits and existing SDRAM memory controllers did not support this data bus width. An existing SDRAM memory controller was therefore modified to support memories with a data bus width of 16-bits. Furthermore, no IP core was available for the LCD module on the Altera Cyclone-II DE2 board. An IP core was therefore implemented for this display. A software package, written in C code, was implemented for communicating with the LCD IP core. The purpose of this software package was to give users of the template design an easy way to communicate with the display. The project was carried out at Aeroflex Gaisler AB and all implementations were successfully verified.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/146808
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectInformations- och kommunikationsteknik
dc.subjectDatorteknik
dc.subjectInformation & Communication Technology
dc.subjectComputer Engineering
dc.titleDeveloping a LEON3 template design for the Altera Cyclone-II DE2 board
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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