Brain modelling with reconfigurable acceleration

dc.contributor.authorZakernejad, Reza
dc.contributor.authorSoleimanifard, Roozbeh
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.description.abstractIn this thesis we port a brain cell model into the Maxeler machine and improve performance while using the advantage of re-configurability of this machine. Hodgkin-and-Huxley model is used in this work to simulate the behavior of certain type of neurons called Inferior Olive [1]. Currently general-purpose machines are able to simulate a few tens of brain cells at (brain) real-time performance; the goal of this thesis is to improve performance by an order of magnitude. That is to simulate hundreds of brain cells in real-time which, for human brain, limits the simulation time for each step to 50 μSec. The Maxeler machine uses a powerful general purpose processor in parallel with one or more FPGA cards, together with a powerful compiler and dataflow programming technique. Simulating the behavior of a network of cells has three main challenges. First of all it is computationally intensive due to the accuracy of the model and thus complexity regarding hardware implementation (on FPGA). Secondly, there are data dependencies between different simulation steps, which require special attention in our dataflow computing model. During the thesis work different solutions have been developed to reach the fastest way to transfer intermediate results from one simulation step to the next. The last challenge comes from the fact that, it is desired for this simulation to support all-to-all communication between the simulated network cells. Thus each cell in a network has to have the potential to connect with any other cell. By using a Maxeler machine as the platform, implementing computationally intensive parts of the model on FPGA and taking the advantage of fully pipelined execution and the parallelism, the performance has been improved by more than x3046, x253 and x4 comparing to MATLAB, C code and other FPGA implementations respectively.
dc.subjectData- och informationsvetenskap
dc.subjectComputer and Information Science
dc.titleBrain modelling with reconfigurable acceleration
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
local.programmeEmbedded electronic system design (MPEES), MSc
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