Design and Evaluation of Efficient Power Amplifier Architectures for Millimeter-Wave 5G Backhaul Applications

Abstract

The rapid global rollout of 5G mobile communications has put a great strain on millimeter-wave backhaul infrastructure, requiring power amplifiers (PAs) with high output power, high efficiency, and wide bandwidth. This thesis presents the design and simulation evaluation of an efficient Class AB power amplifier for 5G point-topoint backhaul links in the 37–40 GHz band. The design is implemented using the United Monolithic Semiconductors GH10-10 Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) process design kit in the Keysight Advanced Design System simulation environment. The methodology makes use of a two-stage cascaded architecture with a driver stage and a four-transistor parallel power amplifier stage. To bridge the gap between the theoretical performance and physical realization, the design incorporates the electromagnetic (EM) model-based layouts for the input, interstage, and output matching networks. The integrated RC stabilization networks were also optimized to suppress low-frequency and out-of-band instabilities, which are common in high-gain GaN devices. The final EM-realized MMIC simulation results show a saturated output power of 34.6dBm (2.9W) at 37 GHz and 33.15dBm at 40GHz. The design exhibited a peak Power Added efficiency (PAE) of 25.93% and 10 dB output power backoff PAE of ∼ 5%. The small-signal performance shows gain (S21) ranges between 11.3 dB and 12.1 dB over the bandwidth and an input return loss (S11) better than 13.6 dB. The final MMIC is found conditionally stable from 1 to 50 GHz with Rollett stability factor also using advanced stability verification with Ohtomo loop gains and Kurokawa driving-point admittance. The results validate the effectiveness of GaN HEMT technology to construct robust and energy efficient transmitter front-ends for next-generation 5G backhaul infrastructure. These results are lower than the design goal and can be improved in future work by adding an additional driver stage or by increasing the total gate periphery of the driver-stage transistors to provide a higher drive capability. Such changes would require re-design of the matching networks to compensate for increased device parasitics.