Static Complex-Response Characterization of Selected ZCU216 RFSoC Loopback Paths at 3 GHz

Abstract

Modern wireless communication systems, particularly 5G networks and radar applications, demand exceptional hardware performance to meet increasing data-rate requirements and to support complex modulation schemes. Practical implementations inevitably suffer from hardware imperfections, including non-linear characteristics in digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), which degrade signal fidelity. While advanced spatial processing techniques such as digital beamforming provide the overarching motivation for understanding these impairments, the fundamental prerequisite is a rigorous static characterization of the data converters themselves. This thesis characterizes the static complex-response of selected loopback paths on the AMD Xilinx Zynq UltraScale+ ZCU216 RFSoC development board operating at a single-tone frequency of 3 GHz. The completed work comprises single-tone end-to-end loopback measurements of seven distinct DAC-to-ADC paths, the generation of a 28 × 16 two-dimensional full LHS map for a single selected path, and the development of a forward GPR interpolation model using MATLAB programming language. It is explicitly noted that the measurements represent the complete uncalibrated DAC-to-ADC loopback cascade, encapsulating analog interfaces, cables, timing, and software processing. The thesis establishes a forward interpolation model and provides quantifiable metrics on amplitude and phase response deviations. No inverse digital pre-distortion was implemented, nor was beamforming or communication-link performance evaluated. This work provides the foundational mathematical forward-modeling framework necessary for future hardware imperfection mitigation.