Power Gating of the FlexCore Processor

Abstract

The aim of this master thesis work is to reduce the leakage power of the FlexCore processor by applying one of the most effective leakage reduction techniques, power gating. The main principle of this technique is inserting transistors named power switches, to cut off voltage supply of the functional units when they are not in use. In the context of this thesis, multiplier unit of the FlexCore processor, a novel architecture for embedded systems, is selected to be power gated. This is because, initial studies show that the multiplier, due to its relatively large size and significant idle time leads to it being a major contributor to the leakage power dissipation. A process of applying power gating onto the FlexCore's multiplier is divided into two parallel branches, software analysis and hardware implementation, and concluded in an integration phase. The software analysis phase, using FlexTools tool-chain, involves profiling of two EEMBC benchmarks and extending of the Native Instruction Set Architecture (N-ISA) to adopt control bits that are enable to activate or deactivate the multiplier unit on demand. The hardware implementation phase focuses on the implementation of the power gating technique by using power specification which is defined in the Common Power Format (CPF) at both RTL level and physical level. In the final phase, the extended N-ISA instruction is applied on the FlexCore processor with power gated multiplier unit to estimate the power reduction at a small area cost. During the physical implementation phase, the optimal power savings were estimated taking in to account the overhead from the switches. For the two examined benchmarks, energy efficiency was shown in range of 4-14%. In real applications, the multiplier is less active than in the benchmarks considered here and thus, it is possible to achieve higher energy reduction.