Interfacing the Xilinx SP601 Spartan 6 development board to the GRLIB IP library

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dc.contributor.authorWinsten, Mattias B
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T13:17:52Z
dc.date.available2019-07-03T13:17:52Z
dc.date.issued2013
dc.description.abstractThis report provides a detailed description of interfacing the developing board "Spartan 6 SP601" with GRLIB's standard IP library. The thesis was carried out at Aeroflex Gaisler at Kungsgatan in Gothenburg. The main part of the thesis consisted of designing a wrapper interfacing the Xilinx Memory Controller Block (MCB) with the Advanced Microcontroller Bus Architecture (AMBA). AMBA is a processor bus architecture developed by ARM for on-chip communication in embedded microcontrollers. GRLIB is a standard IP library (available with GNU General Public License) using AMBA for internal communication. The MCB is a hard circuit within the Xilinx Spartan 6 FPGA that is available through Xilinx's Core Generator software. The MCB is connected to 128MB DDR2 memory provided by Elpida. A board specific template design was created including a Leon 3 processor, AHB controller, IP blocks for reset and clock generation and SPI memory controller, all IP components within GRLIB IP library. During logical simulation a patched SecureIP block from Xilinx was used to simulate the MCB's physical part. The developing language was VHDL (hardware description language), and logical simulation was performed with Modelsim 6.5e. Xilinx ISE developing tools were used for the synthesis and Impact was used downloading the design into the FPGA. Gaisler's GRMON software was used to debug and verify the hardware. Benchmarks and verification was carried out using a set of benchmark programs including Dhrystone and self-developed test software.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/185029
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectData- och informationsvetenskap
dc.subjectComputer and Information Science
dc.titleInterfacing the Xilinx SP601 Spartan 6 development board to the GRLIB IP library
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
local.programmeIntegrated electronic system design, MSc
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