A Scalable Interconnection Architecture for Future Many-Core Systems

Abstract

In this thesis, a scalable interconnection architecture for many-core systems is proposed and the tradeoffs in the design of this architecture are described. Using this model we investigate how the other aspects of network architecture like routing strategy, routing algorithms, buffer space and traffic pattern impact the performance of interconnection network. This report also discusses the simulation environment and the trace-driven simulation approach used for the simulation. The traces are obtained from NAS parallel benchmark using the MPICH application. The simulation is performed for two network models 2-d MESH and CMESH. These models are then subjected to two different approaches of traffic injection: inject as fast as you can, and follow casual order for the injection. The performance of these network models is then compared for the worst case scenario: inject as fast as you can, network backpressure maintains the flow of traffic into network. The variable message size, buffer space and routing algorithm are the variables for which the network performance is measured. This study shows that the choice of network architecture depends upon the priority of the network design. Had it been just achieving lower average message latency regardless of area occupied, power consumed and requirement of buffer space, MESH is a better choice. On the other hand, for the on-chip interconnection architecture where space, power constraints and bufferspace plays a major role; CMESH presents a better choice with the expense of little more router computation complexity and greater average message latency.