Optimized Register File Implementation

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dc.contributor.authorHasan, Ali
dc.contributor.authorVijayashekar, Akshay
dc.contributor.departmentChalmers tekniska högskola / Institutionen för data- och informationsteknik (Chalmers)sv
dc.contributor.departmentChalmers University of Technology / Department of Computer Science and Engineering (Chalmers)en
dc.date.accessioned2019-07-03T12:38:46Z
dc.date.available2019-07-03T12:38:46Z
dc.date.issued2011
dc.description.abstractThe register file is a critical component in any CPU design. As it is accessed almost every cycle, it contributes significantly to key chip characteristics. It is a vital component to optimize for best performance, area and power dissipation. The purpose of this thesis is to implement a full custom, low power and area efficient register file for an Atmel 32-bit microcontroller. The benchmark design is a flip-flop based register file. This thesis work is carried out in two phases – Literature study phase and Implementation phase. During the literature study phase, a number of cell topologies for SRAM based register files were explored. A few different cell topologies were selected for implementation and the power dissipation was estimated. Apart from different cell topologies, different register files architectures such as time-multiplexed and partitioned register files have been implemented. Simulation results show that significant area and power savings can be achieved by designing a SRAM based full custom register file, instead of making a design based on flip-flops.
dc.identifier.urihttps://hdl.handle.net/20.500.12380/143673
dc.language.isoeng
dc.setspec.uppsokTechnology
dc.subjectInformation Technology
dc.subjectInformationsteknik
dc.titleOptimized Register File Implementation
dc.type.degreeExamensarbete för masterexamensv
dc.type.degreeMaster Thesisen
dc.type.uppsokH
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