SEU Mitigation Techniques for Advanced Reprogrammable FPGA in Space

Abstract

FPGAs are becoming increasingly attractive for use in space applications due to their reconfiguration and signal processing capabilities, as well as their increasing speed and capacity. Traditional SRAM-based FPGAs, however, are highly sensitive to the ionising radiation environment in space, making them prone to radiation-induced memory upsets. In this thesis, design techniques for mitigating such upsets are implemented, tested and evaluated, with the purpose of enabling a replacement of conventional radiation-hardened or antifuse FPGAs with Xilinx commercial SRAM-based FPGAs. A test framework using an exchangeable payload is developed for this purpose and run on a Xilinx Virtex-5 FPGA. A payload application is selected and used to test and compare the gains and costs related to different levels of redundancy and different FPGA configuration memory scrubbing methods. In comparing soft error mitigation methods, test results for availability, resource usage, mean time to failure and faults in time are considered. Realistic satellite orbit and radiation scenarios are considered, and a complete example application is presented. The product of this work is a set of recommendations regarding the use of commercial SRAM-based FPGAs in space applications.