Embedded hardware/software co-design methodologies for radar signal processing on multiprocessor system-on-chip
Examensarbete för masterexamen
This thesis investigates diﬀerent embedded design methodologies for hardware/software co-design on multiprocessor system-on-chip (MPSoC) for radar signal processing. Two methods were introduced and investigated to perform the co-design between the processing system (PS) and programmable logic (PL) in the MPSoC. The ﬁrst method was investigated to establish an eﬃcient register-transfer level (RTL) generation tool, which was intended to be part of a complete co-design tool-chain. The second method was investigated with one particular tool, SDSoC from Xilinx, which is developed to support all aspects of co-design in one single solution. In this project we concluded that Vivado HLS is suitable for RTL generation and could be used as part of a tool-chain for co-design. We estimated that by using Vivado HLS the total development time to realize functions as RTL decreased by approximatly 50 % compared to when implemented using HDL. Additionally we concluded that SDSoC is an eﬃcient tool to implement all parts of co-design, including data transactions between the PS and PL. A digital signal processing system (DSP) intended for radar signal processing was implemented and tested on an MPSoC using SDSoC. By utilizing PS/PL co-design a speedup of 23.4 was achieved for the DSP system compared to when only utilizing the PS.
Embedded , Hardware/software co-design , Multiprocessor system-onchip (MPSoC) , Radar signal processing , Xilinx SDSoC , Vivado HLS , HLS tools