Stepwise Pad Driver in Deep-Submicron Technology

Abstract

In this report, we investigate the changes needed to implement a previous design of an energy efficient pad driver in a more modern 130 nm CMOS process, driving a load of 5 pF. A modified design procedure is presented and applied to a test case, resulting in a working driver. Simulations indicated energy savings of up to 50 percent compared to the traditional implementation of a pad driver, at switching times as low as 1.2 ns.