A Method for Estimation of Safe and Tight WCET in Multicore Memory Hierarchies

Abstract

Multicore microprocessors have become the new way to improve the processor performance. Moreover, the multicore processor systems are currently the dominating computer resource in many products like mobile appliances, automotive and space-borne applications. However, the last category’s challenge is that tasks can have various degrees of criticality concerning the response times. Therefore, the aim of this Master’s Thesis is to develop a method to derive a safe (the task execution time can never be longer) and a tight (worst-case execution time is off the real execution time by typically a small factor) worst-case execution time estimates in multicore system with memory hierarchies. The produced method consists of an analytical model and gem5, which is a state-of-the-art computer architecture simulator. This Thesis has surprisingly discovered that the simulated multicore system’s throughput increases by close to linearly with the number of cores. This suggests that, contrary to common belief, it is possible to guarantee a safe worst-case execution time and still enjoy the increase in throughput offered by multicore systems. These findings are therefore encouraging for further investigations. Although, the outcome of this Thesis mainly focuses on LEON4FT, which is a SPARC V8 based System-on-a-Chip, it is also applicable to other multicore systems. Furthermore, the Thesis report introduces the previous studies’ arguments about the transition from uniprocessor to the multicore processors, memory hierarchies as well as worst-case execution time.