Implementation of a Trace Encoder for NOEL-V RISC-V Processors

Abstract

This thesis proposes a solution to the problem of overwhelming trace data production compared to available bandwidth in systems-on-chip in space applications. The proposed solution revolves around compressing the trace data through instruction branch trace, which assumes sequential execution and reduces the trace to instructions and events that result in a non-sequential instruction flow. Given full compilation of a program at the receiving location, the instruction flow of the traced program can be fully reconstructed.

The thesis compares two known trace standards (Nexus and E-trace), and concludes that E-trace is the preferred standard for the stated problem, due to its higher potential compression rate. The thesis then presents an implementation of the trace data encoder in VHDL. The implemented encoder is fed by instruction trace from Spike RISC-V simulator running a test suite, and the correct encoding of the trace is proven through correct reconstruction of the instruction flow by a third-party decoder. The resulting compression rate in a worst case scenario indicates that a 12 core system could be traced simultaneously in a 100 MHz dual-issue system, given a high-speed link bandwidth of 6.25 Gbps. The encoder is then successfully integrated into Frontgrade Gaisler RISC-V implementation NOEL-V. Through synthesization, the thesis shows that the encoder does not introduce a new lower limit on the attainable clock frequency of the processor. Furthermore, the synthesis shows that the encoder falls within a reasonable boundary of the total available hardware in the chosen FPGA. The thesis concludes that the proposed solution to the trace data problem in space applications is valid and realizable.