Advanced Synthesis ECOs with Gate Array Fillers

Abstract

Engineering Change Orders (ECOs) are commonly used in the Application Speci c Integrated Circuits (ASIC) industry to either x design bugs or to add new features to the design after rst tape out. Due to rapid increase in the design complexity the metalmask ECOs have become inevitable. Generally, redundant standard cells, known as spare cells, are used to realize such type of ECOs. However, these cells su er from a major drawback of having prede ned functionality and location [1]. As a result, their use becomes limited. To overcome this in exibility, gate array type spare cells are used. As the gate array spare cell is con gurable, it opens up new possibilities of doing big ECOs. On the other hand, most ECO algorithms o ered by the commercial tools are not smart enough to handle such type of ECOs. In order to overcome this limitation, designers prefer using conventional ASIC ow rather than realizing such big changes as an ECO. In this thesis, a methodology to implement large scale ECOs is presented. This methodology aims to overcome the existing limitations of using the ECO algorithms by incorporating conventional ASIC ow algorithms to perform an ECO. The methodology has been implemented using gate array type cells. Simulation results show that for a medium sized design (12k gates) the implementation consumed 60% more dynamic power and occupied 75% more area as compared to the using regular standard cells. However, if a proper gate array library containing all the required cells is used for mapping, this number would be reduced to 30% and 35% respectively. On the other hand, due to advantages like faster time to market and small manufacturing costs [2] the area and power overhead incurred get compensated.