Performance Evaluation of SYCL on RISC-V Vector Architectures

Abstract

This paper explores the vectorization capabilities of different SYCL compilers, targeting processors with RISC-V Vector Extension, RVV. The primary aim is to evaluate the readiness of various SYCL backends of the AdaptiveCpp SYCL compiler, namely the OpenMP JIT, OpenMP AOT and OpenCL backends. We detail how each approach compiles to RISC-V assembly code, examining how vector instructions emerge or fail to do so across different these different compilation methods. A major part of the work involves discussing how SYCL backends can be configured or adapted to target RVV through toolchains such as LLVM, while also pointing out limitations in support. To support our investigations, QEMU, a general purpose emulator, was used to compile and run RISC-V binaries, and RAVE, a QEMU extension, was used to log instructions executed. These tools were essential in validating whether vector instructions are generated, but also to validate that they are executed. The results show that support for RVV across the ecosystem remains fragmented. Portable Computing Language does not support RVV, nor does it aim to. OneAPI construction kit shows signs of RVV support as vector instructions appear in assembly, however RAVE traces confirm that actual execution does not occur. LLVM offers solid RVV support, but using it with AdaptiveCpp requires modifications to enable full vectorization. In conclusion, although support for RISC-V vectorization is progressing, the broader SYCL ecosystem and its heterogeneous compilation pathways remain underdeveloped, requiring significant manual effort and tooling adaptation to achieve practical performance portability.