FPGA-basedWordlength Evaluation and Optimization for ASIC Implementation

Abstract

DSP designs are widely implemented by fixed-point representations for the consideration of hardware resource utilization. However, determining appropriate fractional wordlengths for signals is difficult as it requires balancing accuracy and hardware cost. Traditionally, wordlength optimization (WLO) problems are solved by simulations to estimate signal accuracy, but this process can be slow for complex DSP designs. To achieve fast convergence speed in more intricate DSP circuits, we propose a modified variant of the tree-structured Parzen estimator (TPE) algorithm, which is commonly used in hyperparameter optimization. By streaming data in hardware, FPGA emulation significantly outpaces software simulation. Therefore, we introduce an FPGA-accelerated WLO system utilizing FPGA emulation. We implemented our system on three DSP designs: two finite impulse response (FIR) filters and one phase recovery design. The results show a dramatic reduction in evaluation time for signal accuracy, achieving speedup factors of 504 for the 29th-order FIR filter, 342 for the 14th-order FIR filter, and 487 for the phase recovery design.