Hardware BVH builder based on the PLOC++ algorithm

Abstract

The demand for high-quality visual effects in 3D rendering of real-time applications is on the rise. To meet this demand, researchers have focused on integrating ray tracing support into graphics hardware. However, support for dynamic scenes still poses a significant challenge. This is due to the fact that the underlying spatial data structures, most commonly the bounding volume hierarchy, must be rebuilt every frame in the worst case. This thesis introduces a hardware accelerator for the construction of bounding volume hierarchies. The proposed hardware is based on the state-of-the-art PLOC++ algorithm, and aims to address the memory-intensive construction through a bandwidth economical approach where most external memory traffic is converted into on-chip streaming traffic similar to PLOCTree [Viitanen et al. 2018]. The proposed unit is on average 2.19 times faster in simulation, with a 3.94 times improvement in memory traffic.