Real-Time Signal Processing Implementation for 100 Gb/s Fibre Communication

Abstract

With ever increasing demands on transmission rates, new ways of transmitting data through fiber are being researched. Up until now on-off keying has sufficed, but this modulation technique has limitations in terms of transmission rates. Complex modulation techniques like 16-QAM allow for much higher transmission rates, however, the computational burden will increase drastically at the receiver's end. The main focus of this thesis is a feasibility study of implementing a 16-QAM 112-Gb/s DD-equalizer on an FPGA, considering throughput, area and power dissipation. The approach used was to gradually change the algorithm in MATLAB to account for different hardware limitations of current FPGA technology. System functionality was proven in terms of BER. In this process, a method for compensating the limitation of phase feedback delay was devised. Simulations of the equalizer in MATLAB show that the algorithm is compatible with current FPGA technology. FPGA mapping of the equalizer parts indicate that speed and area constraints can be met. Power dissipation should be further explored and optimized.